Research And Implementation Of Key Technologies For YHFT-Matrix Compiler Based On GCC

YHFT-Matrix is a kind of high-performance DigItal Signal Processor (DSP) with independ-ent intellectual property right. It is supported by the national project, and designed by Institut-e of Microelectronics of Computer College, National University of Defense Technology. The pr-ocessor is mainly used in wireless communication field of soft-base station. It is essential to p-rovide a high-perforance compiler to support the wide use of the YHFT-Matrix DSP pro-cessor. Because of its special architecture and innovative instruction sets, the existing DSP com-pilers are not suitable for the YHFT-Matrix DSP. So it is necessary to develop a kind of individ-ualized compiler.Because of using the VLIW architecture, the behaviour completely depends on the st-atic instruction sequence obtained by compiler. So the effort of the compiler determines theperformance of the YHFT-Matrix DSP processor. This paper focuses on the research a-nd implement on several key technologies for YHFT-Matrix DSP compiler, according tothe architecture and instruction sets. The main contributions of this dissertation are as fo-llows:1. The instrcution scheduler for YHFT-Matrix compiler is designed and realized.YHFT-Matrix has a VLIW architecture, which means that the width of theinstruction word is variable and there is no fixed slot in the instruction word. And thepipeline of the DSP is not consistent with the current mechnism of instrcutionscheduler in GCC. According to the charactics of the hardware, two modules, one forinstruction word division, the other for execution unit allocation, were added to theYHFT-Matrix compiler’s instruction scheduler based on the list schedulingalgorithm. The result indicated that the instruction queue dealed with the instructionscheduler can generate the paralleled instructions and it meets the requirement of thepipeline.2. Design and realization of register allocation for the YHFT-Matrix compiler. Theprocess of the register allocation in GCC was analyzed and according to thearchitecture, the register allocation for the YHFT-Matrix compiler was realized,including the register pairing algorithm and the priority algorithm for the16-bitsinstructions. There is a one-to-one relationship between the base register and theindex register in our architecture, which is different with the register allocationalgorithm in GCC. The register pairing algorithm was realized by modifying thereload algorithm at the reload process. Moreover, YHFT-Matrix has both the16-bitsand32-bits instructions and in order to improve the code density by increase the ratioof16-bits instruction, we proposed a strategy that some registers have prority in theregister allocation. The result demonstrated that the16-bits instructions have apriority in code generating and the code density can be increased. 3. Design and realization of the address-folding algorithm for YHFT-Matrixcompiler.There is difference in computing the address expression between theYHFT-Matrix DSP and GCC. We modified the form of address expression atmulitple stages in GCC. The result indicated that these modifications can workcorrectly and the generating code meets the requirements of hardware.