Design And Implementation Of OVM-Based SoC Verification System

With the significant increasing of size and complexity of SoC design, the functionverification is becoming more and more complex and difficult. The verification work isconsuming up to70%efforts or even more of the whole SoC design, and has becomethe main bottleneck of SoC design. Therefore, the way to shorten the productdevelopment time, reduce the verification time and improve the efficiency and qualityof verification is becoming more and more urgent. To improve the efficiency ofverification, a verification system with the character of high abstract level, strongreusability and high automation is in great need.The thesis focuses on the emerging verification methodology OVM (OpenVerification Methodology), this verification methodology is an advanced one, whichhas integrated many advantages of the common verification techniques, such as TLM(Transaction-Level Modeling), assertion-based verification and CDV(coverage-drivenverification). These characters have met the requirement of high efficiency, highcoverage rate, high automation and strong reusability. In this paper, not only the OVMcomponents(OVC) and the class library but also the communication mechanism andthe connective mechanism have been analyzed and researched deeply.What’ more, based on the understandingof the structure and functionof the TraceSystem, the paper has built up a verification system with the guild of OVM. Accordingto the specific validation scenarios, a detailed verification process has been carried out,by using multi verification methods, such as TLM, assertion-based verification andCDV(coverage-driven verification). Finally, the results have been analyzed andsummarized, and it is proved that this verification system has strong reusability andself-check ability, and can implement the accuracy error location and coverage-drivenverification, which has greatly improved the efficiency of the verification.