The Implementation And Verification Of The1553B Bus Monitor

MIL-STD-1553B bus is a kind of the command/response type multiplex databus. There are three terminals on the1553B bus: BC, RT, MT.This thesis realizes a soft core of a1553B bus monitor on a particular1553Bprotocol chip. Firstly the research background of the1553B bus monitor isintroduced, then the1553B protocol is analyzed, based on which the function ofthe1553B bus monitor need to be achieved is analyzed, finally the overall designis completed, and each small module of the design is described.After the design, the module level and virtual platform level verification isdiscussed. Firstly the verification platform and test case development are introduced,then according to the simulation steps, the simulation is done, the simulation results areanalyzed in detail, and the code is continuously revised, according to the problemsdiscovered in the simulation, until it meets the design requirements.Monitor soft core’s independence of BC/RT is a feature of the design. BC,RT, MT are designed together forming BC/RT/BM intellectual property on themarket. In the project this paper involved, the design of BC/RT before the projecthas been matured, only the MT’s design is lack. So the design cycle is greatlyshortened by this method.