SiC VDMOS Device Design And Research Of Interface Trap Effects

Silicon carbide （SiC）, due to its large band gap, high critical breakdown electricfield, carrier saturation velocity and thermal conductivity, has been the best choice forfabrication of high-frequency and high-power semiconductor devices. SiC can beprocessed to grow a layer of high-quality thermal SiO₂, while as a kind of promisingpower device, VDMOS has the ability of blocking high voltage and conducting largecurrent with integrated vertical grown cells, being a hot issue around the world.However, physical models in present main device simulation softwares are set forthe default Si material, making the design and verification of SiC devices very difficult,thus development and commercialization of SiC power devices is greatly hindered.In this thesis, major work is based on Silvaco, a popular semiconductor devicesimulation software. With a deep comprehending of related electrical characteristics ofSiC, adjustments and modifications of carrier mobility and impact ionization models inatlas are carried out. Furthermore, taking account of interface state issues, partlyevaluated by a measuring method named charge pumping, C-Interpreter tool in atlas isapplied to define a distribution of interface traps on continuous energy levels. Based onwork above, we realize fitting of simulation data in comparison with measured data, anda reliable simulation platform is established. Using this platform, we verifies a novelSiC VDMOS with optimization of MOS energy band based on the charge balanceprinciple, thus a significantly reduced on-resistance is proved.As a key process in SiC MOSFET fabrication, ion implantation is simulated usingathena. We focus on the Monte Carlo model to optimize the multi-step ion implantationprocess, to get an ideal doping profile and junction depth. Afterwards, completesimulation of the device fabrication is realized, creating an valid device structurethrough atlas verification.At last, application of charge pumping method to analysis of SiC MOSFETinterface properties is introduced in this article, thus an average interface trap density iscalculated. In addition, the relationship between measured substrate current and gatepulse frequency indicates existence of “slow traps” near the SiC/SiO₂interface. Study and achievements in this thesis will effectively help researchers utilize areliable and universal SiC device simulation platform and analyze interface trapproperties effectively. In addition, introduction of a novel device design concept bringsboost of SiC VDMOS performance.