The Design And FPGA Verification Of SATA Controller

With the improvement of the integrated circuit performance and the development of network technology, the data scale is expanded unprecedentedly. The mass storage is becoming an important research topic. On computer’s hard disk, the interference between the signal in PATA interface is increasing with the frequency of the processor continues to accelerate, which can no longer meet the needs of the times. So the serial ATA interface come up with characteristics of less interface pins、 fast transfer rates、 multiple data error correction mode and quick plug.It has become the new darling of the hard disk storage industry since her born. The key technologies are concentrated in the hands of the monopoly foreign companies. It is focused on modifications and secondary development domesticly. The paper designs the SATA host controller in FPGA for the efficient and convenient data storage because of its gaps in the market.The paper analysis SATA1.0English version in detail and understands its hierarchical structure in serial transmission deeply. From top to down is command layer, transport layer, link layer and physical layer. It uses modular concept of FPGA from top-down to maximize the advantages of parallel design within the framework agreement.The command layer is achieved by the embedded processor MicroBlaze mainly to complete the configuration parameters of the hard disk for read and write operations. The transport layer and link layer complete the package、transmission suspension、 parsing and validation control in frame.It is divided into the control module and the data path for function. The former is written in hardware description multi-language VHDL with state machine cooperative implementation, the data is stored in FIFO with CRC and scrambling. The physical layer is achieved by high-speed serial transceiver with the OOB control module and interface transfer rate selection module. High-speed serial transceiver in the corresponding on the analog front end can be flexibly configured according to the needs such as8B/10B encoding and decoding, serial-to-parallel conversion, COMMA character detection, clock correction, pre-focused and linear equalizer options. The OOB control module and interface transfer rate selection module can recognize the hard disk interface transfer rate switched from1.5Gbps to3.0Gbps automatically.The entire design uses Xilinx ISE software for simulation and results analysis.The paper uses Xilinx Virtex-5development board for system verification. The SATA controller is encapsulated into IP core and hanged on the PLB bus.Then it can be interconnected with the MicroBlaze core.The MicroBlaze interacts with command parameter with the PLB bus and deliver commands to the SATA controller for reading and writing tests. The results are consistent with the agreement.Throughout the SATA controller on FPGA with high portability, good engineering research and market value, is of great significance in the field of computer storage.