Design And Verification Of PCIe Bus Physical Layer

PCI Express is a high-performance, general-purpose I/O interconnect bus defined in a variety of computing and communications platforms, is currently widely used high-speed serial transmission standard. Its high-speed data transfer rate makes it extremely broad prospects for development. The physical layer as PCI Express basic underlying transport structure occupies a pivotal position in the entire structure of PCI Express. PCI-Express bus physical layer relative to the major changes have occurred in terms of the physical layer of the PCI bus, PCI Express is a new serial bus. Serial bus data transfer from the parallel bus timing problems faced in the process of high-speed transmission, parallel bus can greatly improve the speed of data transmission.The PCIe bus serial transmission of data, it and the original ISA, PCI and AGP bus, this transmission mode does not have to affect the overall system performance of the play because of a hardware frequency. PCI Express is a working mode known as the "approach of the" voltage differential transmission. Two copper wires, represented by the voltage difference between logic symbols0and1. In this way, data transmission, can support the high operating frequency.The detailed analysis of PCI Express physical layer technology, and focused on several key technologies related to the physical layer, channel alignment technology and clock tolerance compensation relating to the design and realization of the elastic buffer.