Aging Prediction And Single Event Effect Study In Digital Integrated Circuits

As the dimension of the integrated circuit technology shrinking, circuit andsystem reliability become an important issue in circuit design. Aging effect inducedby Negative Bias Temperature Instability–NBTI, and single event effect underradiation environment pose large threat and challenge on the circuit reliability.NBTI can increase delay, leading to timing violation and cause circuit failureeventually. High-energy particles under radiation environment which hit the circuitcan induce single event effect. When the soft errors propagate to the output, circuitfailure will be caused. This thesis focuses on two parts: NBTI induces circuit agingeffect and single event effect caused by high energy particles. The main work andcontributions of the thesis are as follows:(1) In this thesis, an aging-resilient stability checker with on-retention logic,called SCOL, is designed and inserted between a combinational logic output and aflip-flop to predict circuit failure. SCOL can not only detect abnormal time delay ofa circuit, but also store the detecting result without using an additional latch toretain the output signal. The simulation results show that SCOL occupies about37%less area than ARSC and22%less area than ASVFD. Moreover, SCOLconsumes about50%less power than ARSC and40%less power than ASVFD.(2) In this thesis, single event transient on NMOS device is simulated withISE-TCAD. An analysis of the influence of different LET value, incident position,external voltage and circuit connection to single event transient is made.(3) A low overhead hardened flip-flop (LHFF) design was proposed tomitigating D flip-flop single event upsets (SEU). It is a heterogeneous dual moduleredundancy design based on time delay. Spice simulations show that LHFF is SEUimmune. It is also compared to other hardened flip-flops and the results show thatLHFF is superior to the others on the area and power-delay tradeoff.