Design And Implementation Of The Software Simulator For Stream Cores Of Homogeneous General Purpose Stream Processor

Multi-core processors are developing in high speed, from multi-core processorsconsisted of a few complex cores to those consisted of many simple cores. Years agothe heterogeneous architecture, which is made up of CPU and GPU, launched trying tocombine the advantage of both CPU and GPU. However, there is a bottleneck becauseof the separated memorys for CPU and GPU, and the power consumption is high. Thefusion of CPU and GPU on chip is a solution to the long latency of data comunicationbetween separated memorys. But the fusion of heterogeneous processors can not makethe best of the resouce. Based on the background above, the Homogeneous GeneralPurpose Stream Processor (HGPSP) architecture was proposed by our research group.There are a few of homogeneous stream multi-core processors(SM) on a chip in theHGPSP architecture. A part of the SM can be configured to be CPU with the otherbeing configured to be Stream Processor. Shared memory on a chip eliminate the datacomunication overhead between the two parts. The programmability is enhanced by the64-bit RISC cores. The dynamic configuration of the SM function can increase the useratio of resource.Nowadays, the simulators play a significant role in the research for processorsdesign. In the early stage, whether the architecture meet the require of function can bejudged based on the simulators. After finishing the code of RTL model, thehardware-software co-verification could be available. Before taping out, the simulatorscan provide the simulation environment for the upper software, which supports thedevelopment of system software,compiler and application ahead of time. Meanwhile,the statistical information recorded by the simulators contributes to the optimization ofapplication and the reserch for the architecture.Considering the needs of HGPSP research and the significance of the simulators,the paper finished the design and implementation of the simulator for the stream coreMB64of the HGPSP.The main work is as follows:Fisrt of all, the functional simulator of MB64Sim is implemented. It can correctlyload the ELF executable file under cross-endian, perform the branch instruction withdelay slot, register a litter statistical information and provide a experimentalenvironment for compiler design.Second, the performance simulator of MB64Sim is realized based on the dynamicscheduling pipeline with speculation. It uses2-bit branch history table and a branchtarget buffer for prediction and the tomasulo algorithm for dynamic scheduling. Thebranch with delay slot can be accurately simulate. The branch followed by aninstruction in the delay slot and the imm instruction followed by an immediate value instruction are both atomic operations which will never be violated even when therecovery of wrong speculation. Because of the detailed record of the execution and timesequence information, the performance simulator lay a foundation for the architectureresearch.Finally, the paper perform a feature analysis on the size of cache, the associativity,the size of BTB and so on. Contrasting the performance as architecture parameters vary,we can primitively select an optimal compromise one considering the cost of hardware.What is more, the speed of MB64Sim is improved by adopting new techniques of FastForwarding and Dynamic Decode Cache.