Design Of AFDX Swtich Chip Based On Shared Memory

With the rapid development of modern avionics industry and greatincrement of avionics electronic system, the current communication networkhas become bottleneck of the avionics system. As a new kind of avionics datanetwork (ADN) standard, ARINC664defines Avionics Full-DuplexSwitched Ethernet (AFDX), which is based upon IEEE802.3protocol andATM network. AFDX is a high-speed, real-time, reliable and deterministicnetwork. AFDX has found an increasingly utilization in Airbus and Boeing’sproduct, such as A380and B787.Based on the research project “Research of avionics communicationnetwork SOC chip”, this thesis presents the design of AFDX switch chip,meets ARINC664specification, which supports24100Mbps ports and4Kvirtual links, supplies deterministic quality of service guarantee.This thesis begins with an introduction of the generation of ADN, andpresents the architecture of AFDX network and ARINC664specificationsystematically. And then this thesis gives an effective solution for AFDX switch, and particularly describes the realization of core components,including memory management unit (MMU), descriptor management module,configuration table, and statistics collection. MMU uses paginationmanagement mode of buffer space and allocation of free buffer space; it canimprove the efficiency of shared memory in switch chip. According toresearch of output-queuing scheduling algorithms, low latency prior-weightdeficit round robin (LLP-WDRR) is designed for low latency of AFDXswitch. In the end, with the support of results from code function verificationand FPGA prototype test, it is proved that the AFDX switch chip achieves therequirement predefined.