The Implementation Of BP Decoding On FPGA

BP algorithm is an effective method to compute or approximately compute marginal probabilities. It computes marginal probabilities in a time that grows only linearly with the number of nodes in the system. Because of this, it can solve some complex inference problems. Decoding error-correcting codes is in fact an inference problem. Unfortunately, if code length is very long, traditional decoding algorithm is too complex to realize. In this case, BP algorithm is a very good solution. And it is successfully applied in error-correcting codes and CS. This paper extends the application range of BP decoding, using it to decode rateless code, and realizing the decoder on FPGA.This paper first briefly introduces the background of the paper, then summarizes the research status on LDPC decoding algorithm and its implementation on FPGA, as well as the application of BP decoding in CS. Secondly it introduces some basic concept related of BP through Bayesian Network. Then it sets the BP algorithm based on Pairwise Markov Random Field as an example, elaborating the thought of BP algorithm and its theoretical foundation. It introduces the graph model for decoding and elaborates the BP algorithm based on Tanner Graph. Thirdly, according to the characteristic of the decoding procedure of rateless code, selects the appropriate structure of BP decoding on FPGA. And then establishes PC and FPGA joint debugging platform to test the performance of the decoder. Finally, makes some development on variable node updating module and solves the storage problem brought by the parallel processing of variable node.At last the throughput rate of the decoder reaches36.7Mbps, completely meeting the demand of People’s daily use. The achievements of this paper extend the application range of BP decoding and provide reference design to the implementation of BP decoding in CS.