The Selection And Customization Of Low Delay Sensitivity Of Buffer

With the development of the IC design technology, the buffer s delayvariation(ie,delay sensitivity) influenced by the process, supply voltage and temperatureunder different corners increases gradually in the chip, so that chip s timing is difficultconvergence. Therefore, the key issue how to make the timing closure must beconsidered in the chip design.The research object is the hold time of violation path, After some violations arefixing automatically by ICC(IC Compiler), the others need the timing closure through alarge number of manual operation and iterations among the different corners. In order toreduce operational errors and iterations, we propose low delay sensitivity (LDS)algorithm, which is defined as the LDS algorithm; at the same time, we customize somelow delay sensitivity buffers. The main work and innovation points include:1. The source of low delay sensitivity are made further research, chich include theuse of multi-mode molti-corner and the deviation of PVT and the analysis of transitiontime and load capacitance.2. The LDS algorithm is proposed. In order to determine the appropriate buffer tofix hold time violations, the algorithm traverses all buffers. Through the delaysensitivity analysis based on linear interpolation for buffer chain, a low delay sensitivityof buffer chain is outputted by the algorithm. By the comparisom between the algorithmand ICC for fixing hold time violations, the results shows that the LDS algorithm canfix hold time violations which ICC can not fix automatically, so the timing closure isaccelerated.3. The LDS algorithm is implemented by the combination of TCL language andICC commands, and it includes three procedures which are parameter extractionprocedure, delay calculation procedures and delay sensitivity analysis procedure. Thealgorithm is embedded in the physical design flow. As a result, the iterative time isreduced and the efficiency of design is improved.4. Low delay sensitivity of buffers are customized. Through analysing the PVT(Process, Voltage, Temperature), the threshold value and node current for the low delaysensitivity of buffers and changing the ratio of transistor s width to length, the delaysensitivity is reduced. The simulation results show that the delay sensitivity ofcustom-made buffer is lower than original buffer s, so it is more conducive to fix holdtime violations.In summary, the LDS algorithm and custom-made buffer have been proposed inthe thesis to solve fixing hold time violations. Therefore, the methods reduce theiterations of the design and achieve the purpose of the timing closure.