The Study Of55nm High-Speed And Low-Power2-Port Register File

As an important kind of memory, register file is widely used in high speed core memory and SOC(system on chip). With semiconductor technique entering the Nano-stage, IC process dimensions decreasing and chip integration density increasing, the requirements for high-performance and high-capacity in developing the register file is put forward urgently.For deep submicron technology, the access to register file requires higher speed and higher capacity. SMIC55nm LL process is applied to design a high-speed, high-capacity2-port1024x32bits register file in this paper.Under the worst corner (VDD=1.08V, T=125℃), the system proceeded a simulation using Hsim, Hspice and XPS, the simulation results show that data access time is less than I.Ins, the dynamic power is1.6mW, the static power is0.000438mW,the taped out result shows that, the55nm2-port register files designed in this paper has a wider range in data access time than65nm2-port register files’s, all parameters are beyond our expectation.The job in this article focus on:1, based on the design of SMIC65nm2-port register file, we optimized a new55mm2-port register file which applies two independent sets of data, address and control bus. This article pays more attention to the optimization of peripheral circuits, such as address pre-decoder and sense amplifier, to increase memory performance and achieve the desired design goal. Compared the taped out55nm2-port register file’s parameters with65nm2-port register files’s.2, we use the critical path method to pre-simulate to make sure the design feasibility. The simulation parameters include:data access time, signal setup time and hold time, dynamic power, static power, and so on.3, we propose some new simulation parameters, such as the differential voltage when the sensitive amplifier works,the differential voltage when the feedback clock signal active and we optimize this parameter to analyze the necessity and importance of simulating these parameters.The innovative key points in this article include:1, contrast to the simple track on reading clock of word line direction in SMIC65nm2-port register file,55nm2-port register file designed in this paper employs a track on both direction of word line and bit line, and we improve the old tracking method of word line direction to obtain a larger read margin.2we offer a new proposal to simulate the differential voltage at different time. After simulating the differential voltage with the key-path circuit method, we analyze the necessity and the simulation results.3, this paper seeks a way to modify the peripheral circuit structure to improve performance of the entire register file, which supply an example for further research in register file.This article is divided into five chapters, Chapter Ⅰ introduces the development of register file and the structure of memory cell; Chapter Ⅱ represents the structure of register file, operating principle of memory cell, and optimization of peripheral circuits design; Chapter Ⅲ introduces the critical path circuit method;. Chapter IV is about the simulation results of register file using the critical path circuit method based on chapter Ⅲ; Chapter Ⅴ is the prospect and the summary.