Multi-channel Data Acquisition And Processing System Design And Implementation

CNC machine condition monitoring is a prerequisite for the production and processingof security. Focuses on multi-channel data acquisition and processing technology based onARM&FPGA architecture, elaborated32-channel data acquisition&processing systemdesign process in AM3352and EP4CE10F17C8N processors.Hardware platform design introduces the core of digital circuit design; ADC (AD7655)digital-analog mixed circuit schematic and PCB design, board test results are displayed.Software design with the flow of data, time division multiplexing-based configurableFIR filter design and multi-channel real-time data transfer and storage technologies.Created a master-slave state machine model in the FPGA to achieve16-channel paralleldata acquisition and control functions. Filtering the signal processing used in the method,firstly create FIR digital filter model in MATLAB/imulink and the simulation analysis,ARM dynamic allocation factor for FPGA. Use hardware multiplier to achieve a4-channeltime-occupied configurable FIR filtering, better signal quality test results after filtering.Meanwhile, Multi-channel data in the internal cache order by similar ping-pongmechanism for the operation through the dual-port RAM within FPGA, ARM openedEDMA3transmission channel batch (1024/frames) to read the AD data stored in FPGA.Use variable kernel ring buffer, creating a separate read and write data process to achievethe AD data is written to the time stamp named, fixed-size documents which is automaticallycreated in the removable hard disk. Through add Xenomai to the Linux kernel patches toimprove real-time. In all aspects of the data flow experimental tests were conducted to verifythe passage of a sine wave of the whole process from collection to write to the file.Finally, in the test site, a comparison test carried out by this system and a ripedapplicated equipment, results showed that the final signal quality from this system is slightlybetter than the comparison equipment; through statistics ARM response to FPGA interruptlatency time,4ms meet the design requirements, and can guarantee the system stability.