Design Of Three-level SVPWM Inverter Based On FPGA

The last century80’s, scholars such as Nabae by improving the inverter hardwaretopology to increase the number of output levels, derived from the structure, a variety ofmultilevel inverter based on this idea at the same time, a variety of PWM technology wereproposed and verified, but in engineering application are signal processor speed, handlingcapacity limit. With the high performance signal processing technology and processingtechnology matures, the advantages of the multilevel inverter and active power filter system ishighlighted in APF, static synchronous compensator, middle, high voltage VVVF, flexible ACpower supply system has been widely concerned and become a hot research application of highperformance inverter, has become a reality.Based on the diode clamped multilevel inverter as the research object, the requirementsare discussed in detail the working principle, the inherent problems on the basis of thederivation of multilevel inverter--the neutral point potential unbalance, a comprehensiveanalysis of the advantages and disadvantages of hardware, software and control method in theinhibition of neutral point potential unbalance, control strategy is proposed. This paper--SVPWM method the topological structure of three level inverter is simplified, according to theequivalent circuit model of simplified of time domain and frequency domain, high frequencymathematical model was derived for diode clamped three level inverter; on this basis, then themathematical model of SVPWM algorithm, and corresponding mathematical model is set upSIMULINK simulation model, the simulation and result analysis, introduces the neutral pointpotential unbalance and balance state of the waveform, simulation results show that theoptimized SVPWM algorithm based on look up table is feasible, the algorithm in the firstvector is a vector with seven symmetrical short switch state the combination, with smallharmonic component, torque ripple, the device improves. The advantages of the output voltagewaveform, easy to digital control;Secondly, the design of three level inverter system based on the FPGA hardware circuit,the hardware circuit design is given complete control system and discusses the principle ofeach part; Using Verilog HDL hardware logic language for the part of software design inQuartus II+Modelsim, in the QUARTUS II11.0programmable logic software logical wiring and comprehensive according to the top-down design method of the SVPWM signal generatorof IP kernel, the IP core, the dead a delay module, signal generation module and other modulescore into the time of voltage vector is calculated, finally the program to the EP2C35F484C8Nexperimental development board, a SVPWM signal generator for IP core test verification,verification results show that the algorithm has good real-time, high reliability, meet the systemdesign requirements of algorithm.In short, the diode clamped three level inverter mathematical model research, theconstruction of the hardware system, the software part of the simulation results show that, thesystem of SVPWM three level inverter to realize the design of inverter output voltagewaveform similar to the sine wave, low harmonic content, neutral point voltage balanceimproved technology advantages, can be improved to meet the demand for DC-AC generalindustrial applications, with advanced technology, modulation strategy of digital control,reduce the loss of the system, the real-time control get better realize the advantages, has greatapplication value and broad market prospect.