Digital γ-ray Spectrum Acquisition Research

In recent years, with the promotion of γ spectrum measurement technique, changes in applications, for γ spectrum acquisition also put forward higher requirements, and the application of digital technology to meet.Thesis discusses the design methods and techniques of digitalγspectrum acquisition, including front-end analog signal processing, digital shaping technology, digital pulse processing technology. The following results were obtained:(1) The overall design of the system architecture consists of three major modules: analog signal conditioning circuits, high-speed ADC, FPGA-based digital processing.The analog signal conditioning circuit converts charge signal which come from the probe output to voltage signal that amplitude and baseline level suitable for ADC digitized. ADC real-time sampling, the data digitized incoming FPGA. In the FPGA internally trapezoid shaped, overlap judgment, baseline restored, multi-channel storage and other operations, and ultimately into a multi-channel data, and transmitted via the serial port to the computer.(2) Design of the analog signal conditioning circuit, comprising: a charge sensitive amplifier, a main amplifier, a baseline regulator.Charge sensitive amplifier is designed using op amp AD8065.The narrow Charge signal of the Na I + PMT probe output is converted to voltage signal that rapid increase and exponentially decaying, the decay time constant 3.2us.The main amplifier is designed op amp AD8011.It adjusted amplitude of the signal to the appropriate ADC input amplitude approximately 2V.Baseline adjustment: Input ADC generally requires certain common mode signal, the analog signal will be adjusted to the appropriate baseline ADC input requirements, approximately 1V.(3) AD9244 is used as ADC chip, which has 14 bits and 40 MHz sampling rate.ADC use single-ended input mode and the analog signal in real-time sampling rate of 20 MHz,sampling clock provided by the FPGA’s PLL.Converted digital signal is input FPGA and the FPGA processing.(4) Analysis of the digital pulse shaping advantages relative to analog and digital trapezoid shaped pulse shaping technology.It describes the derivation of the digital trapezoid shaped by Z transform and convolution methods.Convolution method is more stable, easier to FPGA implementation.The use matlab simulinksimulation model, simulate trapezoidal shaped to obtain:(1)implementation method of trapezoidal pulse shaping techniques;(2)The ballistic deficit ofinput signal make flat top trapezoid ramp at the forefront.Extended trapezoid flat top help reduce the impact of ballistic deficit.Later segment of the flat top less affected is suitable for peak acquisition.(3)Reduced shaping time,noise is increasing but in favor of the peeling overlap pulse signal and can be a good Extracting the time information of pulse signal and provides the basis for pile up rejected and the calculation control in FPGA.(5) Research digital pulse processing technology based on FPGA and design sampling control of ADC, trapezoidal shape, calculate control, magnitude extraction, multi-channel storage, command reception, PLL modules.Altera’s CycloneⅡ FPGA as devices.ADC sampling control: control ADC sampling, buffered data stream, and the FPGA clock synchronization.Trapezoid shaping: the fast and slow two shaping channels parallel processing, data of slow shaping channel output for amplitude extraction; data of fast shaping channel for analysis of time characteristics of current data.Calculated control: input data come from fast shaping channel, extract pulse events, analyze the current state data of slow shaping channel to generate baseline acquisition, peak capture, calculate the magnitude of the control signal.Amplitude extract: input data come from slow shaping channel, after data smoothing, receives control signal generated by the calculation control module, generating baseline data, and calculate the magnitude of the peak data.After signal amplitude calculation generate multi-channel address.Multi-channel data storage: The IP core generation width 16 depth of dual-port RAM 1024 as a multi-channel storage area.External use data cleared, data transmission, data written three control module as the interface module, to achieve different functions, a multi-choice, as the interface line control.Data transmission: multi-channel data through the serial port, divided into high and low 8 bits sequentially transmitted to the PC.Data written: the signal amplitude calculation module generates the corresponding channel address was read out data, save at the same address after plus 1.Command received: 16 times baud rate, real-time sampling serial input pin to read data, after identification command, send command flag signal related operations.PLL module: The external active oscillator 10 M clock signal input, multiplier to 20 M, as the master clock system and generates all the way to 20 M output clocks to the ADC samples.The final design results are:board size: 5 × 6 cm;overall power consumption: 0.87W;sampling rate of 20M; resolution: 7.6%; energy linear: 99.99%.It can be used to signal acquisition and processing for scintillation detector.