A Single-inductor Dual-output Buck-boost DC-DC Converter With Digital Extended-PWM Control

There are more and more powerful and affordable smart handheld devices, consumer electronics products in the application nowadays. In the circumstance that the tension was evident in the energy cost competition, power management chips are faced a serious challenge, but it also brings opportunities. Single-inductor Dual (multiple)-output DC-DC converters can significantly save the manufacturing costs of electronic products because of less off-chip inductors, as well, bring convenience to portable designs. On the other hand, since increasing system complexity makes # more demands on the power management unit, as well as the progress of the IC process causes pressure to analog circuit design, highly flexible and intelligent数字 power management chips draw attention of academia and industry of integrated circuits in recent years.In this thesis, the research and design of digital extended pulse width modulation (DEPWM) controlled single-inductor dual-output (SIDO) buck-boost DC-DC converter, based on dc and small signal analysis of power stage, compares various modulation modes and control methods, and combines the basic principles of analog extended pulse width modulation (EPWM) and the advantages of digital control, then proposes the algorithms of digital extended pulse width modulation to achieve the digital design of control loop through system modeling and simulation. Meanwhile, to optimize the characteristics of transient response when large load change occurs, an improved dual-mode digital PID compensator is proposed to replace the traditional one, so that the overshoot (undershoot) and recovery time of output voltage caused by dramatic load change are reduced.To meet the requirements of low power, middle speed and resolution of A/D conversion in digital power management circuits, windowed delay-line A/D converters are adopted to convert error voltage in this thesis. The LSB of A/D is 7.8125 mV with dynamic range from Vref-0.125 to Vref+0.125, together with resolution of 10 bit in DEPWM, this can fit the system operation very well. This A/D converter achieves the low power and fast response while keeps the accuracy since logarithmic and average hybrid algorithm has been applied in the A/D conversion.The chip is designed with CHRT 3.3V/5.0V 0.35μm dual-gate CMOS process, with an input range of 2.5V-5V and output range of 1.2V-2.5V/2.5-5V, the max load current is 400mA in each output. Simulation results show that the proposed DEPWM can realize stable output voltage, and output voltage ripples are controlled in less than 30mV; with the application of improved dual-mode digital PID compensator, the overshoot and undershoot are reduced by about 60% when dramatic load change occurs in a certain output, also the recovery time is shortened by about 50%, while the cross regulation voltage of another output is less than 60mV. The results verify the analysis and innovative design reasonable in this thesis.