Design And Implementation Of Digital Tracking Receiver

As an important part of the remote sensing satellite earth station, automatic tracking receiver receives satellite data from the antenna, through conversion, filtering, amplification, detection and demodulation,provides the required pitch and azimuth angle error signal for servo systems which controlthe azimuth axis and pitch axis of the antenna.Then,the antenna rotates to the direction where the error is reduced until the antenna alignment the target. The IF digital receiver completed the information extraction of IF target signal and complete automatic tracking with the servosystem. Conventional self-tracking receiver primarily analog circuit, there are some inherent drawbacks. With the rapid development of large scale integrated circuits and software radio technology, digital tracking receiver become a trend, and is gradually replacing the analog tracking receiver. the major algorithms in FPGA:This paper describes the main functions of the receiver as well as common species receiver and their respective work in the aerospace mapping systems, and analysis characteristics of various types of work and compare the receiver. Single-channel pulse receiver which because of its many advantages, is widely used in engineering, which has important significance, is the focus of this paper. By analyzing the simulation of single-channel pulse receiver tracking works and performance, combined with modern digital signal processing technology, make the digitized single-channel pulse receiver implementation. In order to verify the feasibility of the program establish MATLAB model and simulate principle. On this basis, further verify the actual project, the specific approach is completing the prototype design of digital receiver on a general purpose digital signal processing platform, and final design a dedicated digital signal processing platform and do porting work to complete the prototype performance optimization, finally complete the entire prototype hardware and software design work, performance of the indicators meets the design requirements and have been test at a communications station. The main algorithm is implemented in the FPGA: first, the analog signal is filtered IF amplification, FPGA control AD sampling timing to achieve direct IF undersampling, high-speed data stream enter FPGA through which contain frequency estimation module, DDS module, FIR filter module, loop filter module, mixer DPLL module and is called the complete phase-locked loop extracte and synchronizate phase. The DSP do automatic gain controling and signal demodulating work. The initial prototype function is not difficult to achieve, but the ability to extract the PLL has been difficult to improve, resulting in strong noise PLL lock is instability, occasionally appearing of unlock, lead the prototype unstability. After a review of the relevant literature, make some adjustments of the initial design of the structure, including the extraction percentage of pre-selected loop filter, FFT frequency estimation point selection, and adjust the loop filter parameters. Some engineering model is very difficult to analyze, the actual project go through a lot of experiments to find the optimal parameters.