Research On Synchronous Messurement Unit In Transmission Line Condition Monitoring System

The monitor system for transmission lines in running state can provides effective 24-hour monitoring about the parameters of the transmission lines and the surrounding environment, which can identify and cope with potential troubles in time. In-time synchronous measurement on phasors in different places requires to synchronously measure the voltage pressure, current phasors at nodal points in different places based on the same time standard to ensure the synchronization of the results, which is of great importance to the evaluation of the running state of transmission lines, the stability control and the trouble identification.There are two issues to be dealt with in terms of synchronous measurement, namely, time synchronization(time synchronization of signals under measurement in different places) and frequency synchronization(frequency synchronization of samples and signals under measurement). By far, the most commonly adopted method for time synchronization is time lag compensation. Yet, it cannot guarantee high accuracy of timing after the satellite is unlocked for 24 hours. Discretization synchronous sampling is most commonly used for frequency synchronization, such as the improved DFD. However, the accuracy and stability still need to be improved.To cope with the issue of time synchronization, a GPS enabled power system of time synchronization based on FPGA is designed and implemented. Driven by the core conception of using average mean to reduce error, the new design framework allows less calculation, smaller FPGA based internal logical module, smaller storage space and more accurate time signal compared to other normal method that employs time lag compensation. To deal with the issue of frequency synchronization, this study proposes to add Hanning window interpolation to FFT algorithm, which therefore consists of three steps: employing Hanning window, polynomial transformation and double line interpolation correction. Based on these, this study proposes the design of a synchronous measurement device, which consists of synchronous clock unit based on FPGA, synchronous data collecting unit based on multi-channel high speed ADC, data buffer memory unit based on “table tennis” operation and DSP data analysis unit. The design rationale and the rationale for the choice of chips in every unit are demonstrated as well.Based on the FPGA and GPS enabled timing design and synchronous measurement, Hardware experiment results show that when the satellite is still locked, the pulse signal error every second could be maintained at 100 ns. After the satellite is unlocked for 24 hours, the pulse signal error can be still maintained at 12μs. The time synchronous measurement results show that compared with traditional FFT and the current algorithm by adding Hanning window interpolation, the algorithm proposed by this study can maintain several orders of magnitudes higher frequency, amplitude, and phase position. When the voltage pressure fluctuates, it can also maintain high stability by stabilizing the error of frequency, amplitude and phase position at the level of one order of magnitude.