Research And Design Of Buck Converter With Segmented Power Mosfets

Nowadays, portable smart devices are experiencing an rapid development all around the world. More and more new functions are being integrated into them continuously while their sizes are decreasing adversely, which leads a huge increase in energy consumption density of electrical systems. Disappointingly the performance of batteries has almost stayed still over the past many years. As a result, endurance time of electrical systems is threatened in being shortened. Therefore improving system energy utilization and extending battery active period has become a research hotspot.Power management ICs play an important role in delivering energy in electrical systems all along. It makes significant sense to improve their energy conversion efficiency. A Buck DC-DC converter whose power MOSFETs are divided into several segments and turned on in turn has been proposed and implemented in this thesis. The technology of segmented power MOSFETs is useful in DC-DC converter efficiency improvement especially in the condition of light load. It balances the conduction loss and driving loss by changing the size of power MOSFETs according to the load current,which minimizes the total loss caused by power MOSFETs and improves conversion efficiency of DC-DC converter.The specific segment scheme in this thesis is as follows: in the mode of CCM,SenseFET current sensor detects the load current and determines control codes of big power MOSFET segments; in the mode of DCM, TDC detects the turn-on time of power PMOS and converts it into control codes of small power MOSFET segments; in the condition of extremely low load current, the converter enters into PSM mode and only one small segment of power MOSFETs is working.The research background of this thesis is described in the beginning, and then the basic theories of Buck converter and the technology of segmented power MOSFET are introduced. Later, modules including current sensor, TDC, and error amplifier are designed and simulated. Finally, simulations, layout, and PCB design of the whole chip are finished successfully. The total area of whole chip layout is 1.45mm×1.28 mm. The chip is implemented under 180 nm standard CMOS process in the end.The simulations indicate that the Buck converter proposed in this paper has a relatively higher conversion efficiency compared to the traditional ones, especially inthe condition of light load. Specifically at 25 mA load current, maximum efficiency improvement of 5.9% is obtained. Finally, efficiency improvement effectiveness of segmented power MOSFETs on DC-DC converter has been proved.