Design Of Interface ASIC For The Capacitive 3-Axis Micro-Accelerometer

A capacitive 3-axis micro-accelerometer is been used for military equipment, automotive electronics, intelligent terminals and other fields since it is small and light, has a high precision and reliability. The performance of chip of the macro-accelerometer and interface ASIC made in China is poor compared with foreign advanced one because of our backward materials industry and microelectronic technology.This paper firstly adopt the structure of circuit by analyzing operating principle of mechanical structure and interface ASIC, noise level and stability of micro-accelerometer with different orders. Then a detailed design of an interface ASIC for a capacitive 3-axis micro-accelerometer is presented. The acceleration of 3 axes can be detected simultaneously with the same circuit by using discrete-time multiplexed technology. The resolution of C to V is enhanced by using correlated double sampling. Using Sigma_Delta modulation technology can reduce the circuit noise. The interface ASIC is composed of different modules of C to V circuit, sampling and holding circuit,2-order Sigma_Delta ADC, force feedback arrangement, band-gap reference, logic circuit.The simulation results of the system and layouts of some important circuits are presented in CSMC0.5um CMOS process. With a capacitive 3-axis accelerometer, the measured resolution of the system by simulation is 0.91 aF/Hz1/2, and the noise floors in the x-, y-, z-directions are 43.60μg/Hz1/2,43.60μg/Hz1/2, and 45.70μg/Hz1/2, respectively. The nonlinearity of duty cycle of 3-axis digital output is 1.38%,0.91%, and 1.79%, respectively.