Reseach On The Characteristics Of Memristor And Its Application In Neurological Network

In recent years, because of the memory of resistance, threshold characteristic, low power consumption, simple structure and a series of advantages, memristor attracts many researchers around the world. Typical memristor structure is a sandwich structure: top layer and bottom layer are conductive metal layers, act as two electrodes connected with the outside world. The middle is an insulator, typically a transition metal oxide material. Typical memristor has three processes: electric forming process(FORMING), setting process(SET) and resetting process(RESET). The so-called FORMING means: a memristor can achieve low-high resistance switching function after the material excitation process; the so-called SET means the process that memristor state changes from high resistance state(HRS) to low resistance state(LRS); the so-called RESET means the process that memristor state changes from low resistance state(LRS) to high resistance state(HRS). By the polarity of the applied SET voltage and RESET voltage, the memristor can be divided into unipolar memristor and bipolar memristor: If the SET voltage and RESET voltage are the same polarity, the memristor is unipolar memristor; if they are different polarity, the memrisotr is bipolar memristor. Memristor resistance value can be programmed by external voltage or current. Because of these remarkable features, memristor has been widely applied to the memory, digital circuits, analog circuits, RF and microwave circuits, chaotic circuit and artificial neural networks. this paper mainly studies on the memristor further applications in artificial neural network and proposes a programmable neuron circuit for analogging biological neurons and designs out a discrete hopfield neural network circuit.This paper firstly studies the principle and structure of the two novel circuits, then uses Cadence to simulate the circuits to verificate that the circuit structures are correct or not. Finally, this paper builds up a board-level discrete hopfield neural network circuit and then tests the board-circuit. Whether Cadence simulation results or the board-level test results, all obviously reflect that the designs of the circuits are feasible and have practical feasibility of an integrated implementation. The designs will be a good guide for the hardware implementation of artificial neural networks.