Low Power Optimization Technology For Loop Codes Of Software Fault-tolerance Based On DSP

In recent years, with the development of science and higher performance requirements of computer, it has become the development trend both at home and abroad to adopt commercial-off-the-shelf(COTS) to build the space equipment. Compared to the traditional chips used in aerospace, COTS have the advantages of high performance, low costs, and abundant quantities and so on. It can satisfy the growing performance requirements of the aerospace equipment.There is bad environment of the electromagnetic noise, such as high energy particles irradiation, voltage disturbance and electromagnetic interference in space. The inadequate conditions make the reliability of the satellite-borne computer become a very serious problem. COTS have the low ability of radiation resistance. The defect makes COTS irradiated by high energy particles easy to malfunction in bad space environment. Therefore, it must improve the ability of COTS to resist radiation in space applications. Carried on the thorough research on this, it has made some research results both at home and abroad. The effect of the software fault-tolerant technology is extraordinarily outstanding. Without any dedicated hardware, using this technology can also meet the requirements in the reliability of aerospace applications. However, much double calculation in the software fault-tolerant technology will greatly improve the energy of the system overhead. Thus, how to reduce the energy consumption becomes a problem which must be solved in space equipment of limited energy.Due to the technology blockade and military commercial restriction from western countries, it is difficult to acquire anti-radiation chips used in military. Therefore, the software fault-tolerant technology is of great significance to our country’s aerospace development. Meanwhile, under the premise of ensuring the space computer’s reliability, it is the first priority to improve performance and reduce power consumption as far as possible.This paper studies the control flow and data flow of the software fault-tolerant algorithm, and puts forward the optimization strategy of the DSP chip, which is on the experimental platform of the high performance commercial DSP-TMS320C6748 hardware. In this paper, we have done the following works and innovations:(1) Depth study of the software fault-tolerant technology, data flow and control flow fault-tolerant algorithms and power optimization technology, summed up the characteristics of DSP hardware platform designed from soft to soft front reinforcement algorithm until soft after the last three stages, all-round the fault-tolerant software optimized for the optimization of processes.(2) Designed based on C/C++ language and assembly language-based low-power optimization method. In C/C++ language, the for loop code, summed including loop unrolling, loop fusion, loop tiling and other low-power optimization method. In assembly language, for the C6000 DSP unique linear assembly, summed up in line, embedded and other low-power optimization method. Verified by experiment, during the software fault-tolerant processing prior to using the above method to optimize the average performance increase of 36.2%.(3) Analysis of the characteristics of soft reinforcement algorithms and processes, combined with the characteristics of DSP running water, facing the DSP hardware platform, the soft reinforcement algorithm is proposed to improve the linear assembly cycle DSP-based optimization algorithm SFLOA, in order to increase the cost of delay tolerant, without reducing the error detection rate at the same, to more fully utilize the DSP pipeline, significantly reducing the number of run cycles, reducing the total energy consumption. Through experimental verification, fault-tolerant process, use SFLOA algorithm tolerant algorithm can be optimized so that the average power consumption rate reached 79.995%, with an average performance increase of 57.76%.(4) After the soft reinforcement optimization phase, we propose a reinforcement cycle based on soft dynamic voltage scheduling algorithm LFDVS. The algorithm is based on the cycle after a fault as a basic unit, is assigned to each cycle of the processor is not the same frequency, the loop from the complex to the simple cycle static scheduling dynamic scheduling, to ensure the detection error rate conditions, to maximize the use of the CPU idle time to reduce the voltage and frequency of power optimization measures. Experimental data can be seen through the algorithm can significantly reduce the energy costs.