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Development Of FPGA-based Bunch-by-bunch Beam Current Monitoring System At Storage Ring

Posted on:2017-02-06Degree:MasterType:Thesis
Country:ChinaCandidate:C S LiuFull Text:PDF
GTID:2272330485951034Subject:Nuclear Science and Technology
Abstract/Summary:PDF Full Text Request
To multi-bunches storage ring accelerator,bunch-by-bunch beam current measurement is a important way to monitor beams and to study injection filling pattern and beam instability.Besides,it’s a indispensable way to realize top-off injection.Large accelerators such as international Spring-8, BESSY, KEKB, NSLS Ⅱ, domestic BEPC Ⅱ, SSRF, HLS Ⅱ have beam current measurement system.Currently,bunch-by-bunch beam current measurement system of HLS II uses digital oscilloscope to sample the sum signal of BPM,then using integral method to measure bunch current. The sampling resolution of oscilloscope is 8 bit and the sample timing is not synchronous with each bunch,so it needs to use interpolation algorithm to reconstruct signal wave.Because HLS Ⅱ will work in top-off injection mode in the future,so it puts forward a higher precision requirement for the bunch-by-bunch beam current measurement system.In this paper,the author firstly researched bunch-by-bunch beam current measurement solutions of world’s main accelerators, analyzed and derived the bunch current measurement theory, detailed analyzed measurement principle of using stripline BPM and button BPM and also analyzed influence on measurement of longitudinal oscillation and beam elongation effect and the way to solve them. On this basis puts forward a new HLS Ⅱ bunch-by-bunch beam current measurement scheme.Then,this paper introduced the hardware structure of newly developed bunch-by-bunch beam current measurement system.The system is mainly consist of high speed and high precision ADC,high performance FPGA,USB and local PC. The sampling resolution of ADC is 12 bit and the highest sampling rate can reach 250MS/s.The sampling clock comes from RF clock,so the sampling is synchronous with each bunch.The phase shift module in FPGA can shift the sample clock’s phase accurately,so the ADC can sample the signal’s peak value.Besides,a FIFO is constructed in the FPGA to cache the sampling data. USB is responsible for the data transmission to the host to analyze.This paper introduced processing algorithms of sampling data in detail.Data processing mainly complished by LabVIEW software. LabVIEW communicates with EPICS by CA Lab interface to get realtime DCCT current to calibrate bunch current. We can get bunch-by-bunch longitudinal tune by FFT.At last,the newly developed bunch-by-bunch beam current measurement system is taken a online test.The test results show that when the storage ring’s longitudinal feedback is on and the longitudinal oscillation are suppressed,the measurement has a high precision and root mean square error can reach 0.002mA. Besides the bunch-by-bunch beam current measurement, the bunch-by-bunch longitudinal tune is measured by the system, and other potential bunch-by-bunch beam diagnositics could be done in future, like bunch-by-bunch beam life et al., to improve the performance of the storage ring of Hefei light source.
Keywords/Search Tags:Hefei light source, storage ring, bunch-by-bunch beam current, high speed ADC, EPCIS
PDF Full Text Request
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