The Cooperative Control Research Of Cascaded Solid State Transformer Based On DSP/FPAG

Solid state transformer (SST) is considered as the key device in building energy internet in the future, which is play a role as an energy router in the energy internet. What can be achieved by using solid state transformer includes the functions about the access of DGs, regulation of power quality in grid, compensation of reactive power and transmission of power, etc. So solid state transformer is a novel intelligent power electronic device that can advance the building of smart grid and energy internet.The cascaded SST is an improved SST to access high voltage level grid, whose former stage is replaced by a cascaded H-bridge converter. This paper analyzes and studies the theory about the cascaded SST, and uses a cooperative digital processor based on DSP and FPGA to achieve superior control. Finally, the whole system can be controlled stably. The main contents of this paper are proposed as the following:First, the basic topology and principle of the cascaded SST are analyzed, and a mathematical analysis of carrier phase shift technology is proposed. Then three different control stratrgies are used in the three stages of the cascaded SST. A voltage oriented control is used in the rectifier stage, which include internal ac current loop and external dc voltage loop. A double closed-loop control strategy is used in the inverter stage, which include internal ac current loop and external ac voltage loop. The middle stage is control by a fixed duty-cycle control strategy. After that, a two-level cascaded SST model is built and run in MATLAB/Simulink, based on the above control strategies. The simulate result shows that the control strategies are feasible.After the study of theory and the simulation, a real-time digital control platform of the cascaded SST is designed in this paper. There are two parts of this design process. The hardware and software design of experiment system includes the design about main circuit and its assistant circuits. The program of control algorithm in DSP and the program of CPS-PWM technology in FPGA are also included. The hardware and software design of cooperative processor includes the design of communicate bus using SPI protocol and the program of SPI communication in two processors.Finally, the experiments based on the above platform of the cascaded SST are introduced. In the rectifier stage, two inversion experiments in open-loop control strategy, and a grid-connected experiment in close-loop control strategy are proceeded to verify the feasibility and effectiveness of the cascaded H-bridge converter. In the inverter stage, the experiments in single current-loop and single voltage-loop control strategy are proceeded to verify the feasibility and effectiveness of the inverter. Then an experiment in double close-loop control strategy is proceeded to verify the dynamical performance of the inverter. For the isolation level, there is a fixed duty cycle experiment to verify the performance of the circuit. The results of all these experiments show that the whole cascaded SST system is in the stable running and the cascaded SST can be controlled stably and effectively by the cooperative processor based on DSP and FPGA.The simulation of the cascaded SST and the experiments of digital real-time control in the real platform are verify the feasibility of topology and the effectiveness of control strategy, which lay the foundation to achieve the comprehensive digital control about higher voltage and power.