Research On Power Damping Synchronization Control For VSC-HVDC Connected To An Extremely Weak AC Grid

Voltage source converter based high voltage direct current (VSC-HVDC), adopting widely used classic vector current control (CVCC) shows poor operation performance in weak ac system conditions, due to the phase locked loop (PLL) dynamics. Power-synchronization control (PSC), which eliminated the PLL, is proposed for VSC connected to weak ac grid. But the backup PLL is applied to keep the VSC in synchronism with the ac system in order to limit the alternating current flowing through the converter. Combining the technical advantages of CVCC and PSC, the control performance of VSC-HVDC connected to an extremely weak ac grid can be improved.Firstly, the technical characteristics of CVCC and PSC are analyzed, and the double closed control loop of CVCC and PLL are reserved. The inner current controller is designed based on the external mechanical characteristic of synchronous generator and the mathematic model of VSC. By introducing power synchronization loop (PSL) and power damping loop (PDL), a novel power damping synchronization control (PDSC) is proposed for VSC-HVDC connected to an extremely weak ac grid. Then, a small-signal model of VSC-HVDC system based on PDSC is derived. The model is validated via MATLAB and electromagnetic transient simulation program PSCAD/EMTDC. The impact of PLL, PSL and PDL parameters on the dynamic and steady-state behavior of VSC-HVDC system is determined by small-signal analysis for a weak ac system with short circuit ratio (SCR) SCR=1.0. The Feasible region of PSL and PDL parameters and maximum available power (MAP) of VSC-HVDC based on PDSC under different SCRs are analyzed. The small-signal analysis results are validated in PSCAD/EMTDC. Finally, considering the uncertainty of VSC model in an extremely weak ac grid, the outer voltage controller is designed based on auto disturbance rejection control (ADRC). For modular multilevel converter based HVDC (MMC-HVDC) system, a direct circulating current suppressing controller based on the ADRC is designed to depress the circulating current of MMC and a negative-sequence current suppressing controller based on the ADRC is designed to depress the negative-sequence current during a fault.