Research And Implementation Of Global Interconnection Test Based On 65nm

Field Programmable Gate Array can be fast, repeatedly configuration features programmable chips. In the field of medical electronics, image processing, cloud data centers it plays an important role. FPGA can be repeated by a large number of blocks and connect them to interconnect resources, the latter including interconnection line (Line Segment) and programmable interconnect switches (PIP), which interconnect resources abound in the FPGA chip must be used in every configuration, so their test is very important. FPGA interconnection distribution line in the horizontal, vertical channel in both directions; PIP are two main components to connect through a global matrix (Global Routing Matrix, GRM) global switch (Global PIP) in and out of the center and the logical unit (CLB) local interconnect switches (IOMUX PIP). Interconnection lines and switch matrix called global interconnect resources, input and output selection module selection module called local interconnect resources, and research contents in global interconnect test based.A good test programs are usually required to complete almost 100% fault coverage in the configuration file relatively small number of cases. With the increasing size of the FPGA chip, a FPAG may be configured into a number of very large, it is impossible to test one configuration. A simple majority of academic research are targeted FPGA architecture, interconnect single type, interconnected switches can be simply divided into horizontal direction, numeric, left oblique and right oblique four categories, these studies tend to default FPGA chip around IO resources have around. With the continuous development of FPGA architecture, its structure is also more complex, linear diversification has become a trend, there is not a switch type in the four directions, and surrounded by new FPGA chip part is no IO distribution.This paper proposes a new global interconnect test algorithm, sub-line fault coverage, fault coverage and coverage side climb three stages configuration file generation. The first stage uses a connection failure S-line policy coverage, which can effectively reduce the FPGA chip peripheral IO dependence; second stage consideration of factors to consider using a depth-first search algorithm to generate connections to all the global interconnect PIP centrally, without the need to classify the direction of PIP. Breadth-first search for the third stage of the switch is not covered, uncovered resource search target, effectively reducing the required number of patterns. Under the premise of ensuring high coverage, we did a small number of test profiles, low labor participation, the hardware structure and strong adaptability. This algorithm on FDP5P15 chip was tested with 150 test profiles covering more than 90% of chip failures.