Research And Implementation Of Noc-based CMP For Spike Sorting

With the update of CMOS technology and the improvement of internal organization of the human brain research needs, people can insert hundreds or thousands of microelectrodes into the brain to collect brain potential sign als. Currently brain potential signal processing approach use a system which include microelectrode array and the host computer. Collectting and processing more information from the action potential of neurons in the brain help people to study deeply the internal structure of the human brain, to diagnose and to treat diseases of the brain more accurately. The microelectrodes inserted in brains will be surrounded by a lot of neurons, so the collected signals are mixed signals from these neurons, before these singnals to be used, we have to classify these signals. However, using the system a microelectrode array and a host constituted the collection and processing of the data. To deal with these data, it is necessary between the microelectrode array and a PC arranged high bandwidth links, while the host configuration requires a lot of storage resources to store the raw data. Meanwhile, the current peak level classification algorithms are implemented in software on the host, the time required for a long, unable to meet the needs of realtime processing results obtained.From another aspect that the development of CMOS technology, allows us to integrate more transistors on a chip, so that we can achieve more challenging computing tasks on a single chip. On-chip networks have good parallel computing capabilities, in order to solve several problems mentioned above, this paper presents an article on the research of the potential of existing neural classification algorithms, the existing classification algorithms are s ummarized changes proposed a web-based on-chip Spike Sorting acceleration platform that can handle real-time 3 channels collected brain action potentials. Each channel has its own separate circuit, interference between the various channels. Our entire CMP(Chip Multi-processors) of each module were carried out functional verification and synthesis, verification rate of 100%. As experiment results show, after data processing on this platform, the size will smaller than the original data by 50 times, not only reduces the need for link bandwidth, but also reduces the requirement for mainframe storage resources.