Floating-point Multiply-add Fused Unit Analysis And Custom Design Of Mantissa Adder

Floating-point multiply-add Fused (MAF) unit is the core arithmetic component in modern microprocessors; its speed has direct impact on the performance of the microprocessor. The floating-point MAF, in the critical path, has long execution delay, complex structure and relatively high power consumption. Therefore, researches on the floating-point MAF unit are of great important application value.This paper studied and optimized the design of the64-bit floating-point MAF in X processor. Based on the design of supporting floating-point operations and integer arithmetic, analysis and research on the key modules are done. The DC results show that the108-bit mantissa adder of the original design restricts the performance of the entire floating-point multiply-add fused unit greatly. This paper improved the overall performance of the floating-point MAF by improving the structure of the mantissa adder and custom design. The main contribution of this subject is as follows:1. Searching and analyzing the critical path by DC compiler of Synopsys, looking for ways to improve the performance of the whole floating-point multiply-add fused unit;2. Carry select adder and End-Around-Carry (EAC) structure are used in the last two level of the mantissa adder respectively. The carry-chain of "0" and "1" is partly shared in the carry select structure, which reduced the area further, and the performance will not be affected. The EAC structure eliminates the need for binary complement of the addend and the final result;3. At40nm process, the custom design of108-bit mantissa adder is completed, and corresponding timing verification is done. The design occupied an area of1872.82um2, under worst case conditions, and the operation of mantissa adder has a latency of350ps. Compared to the original design, the design in this paper gets a result of20%area reduction and23%performance improvement. Making the mantissa adder out of the critical path, this means that the mantissa adder shall not be the performance bottleneck of the floating-point MAF.