Design And Implementation Of Task Management And Scheduling Mechanism For A Heterogeneous Five-core XDSP

Revolutionary changes have taken place on the development of prosessor designtechnology, Multicore processors instead of single-core processors gradually becomethe mainstream of processor technology. As a branch of the universal microprocessor,Digital Signal Processor (DSP) is also on the highway going to the ear ofmultiprocessor, especially the heterogeneous multiprocessor. DSPs are intergradationsof ICs and applications. Efforts to improve the performance of DSP should be done notonly in the softwares and operating system, but also in IC design. Task management andscheduling is a key point that applications and ICs should pay attention to. The presentof heterogeneous multiprocessor brought a new question to consider to this key point,i.e. which is, what kind of implementation of IC can surport the management andscheduling algorithm and can improve the performance of heterogeneous multi-coreDSP effortly.In a SoC heterogeneous multicore DSP operating system, task management andscheduling runs on arithmetics level. On a lower level, it requires the hardware and thecorresponding drive software. Hardware and drive software are the basement of thewhole task management and scheduling mechanism. Works, that designing andimplementing the hardware and drive software of the management and schedulingmechanism, have been mentioned in this paper are parts of an heterogeneous five-coreDSP design project leaded by the National University of Defence and Technology. Wesummarize out work as follows:Based on the XDSP’s architectural features and on-chip peripherals, wedesigned and implemented the task management and the schedulingmechanism in hardware, supporting communication and control between theMCU subsystem and the DSP subsystem;The drive software is developed tp facilitate using the hardware, including theboot programs under multiple models, interrupt handling programs tp supporttask scheduling and synchronization;Verification of the task management and scheduling mechanism was done atboth module level and system level. Coverage-driven method, assertion-basedmethod, and HW/SW cooperative simulation method are adopted during theverification process;The FPGA prototype of the XDSP was implemented for the sake of verifying.The task management and scheduling mechanism at systematic level. Based onthe FPGA prototype, a JPEG decode program was successfully parallelized byusing the task management and scheduling mechanism.