Research Of Process-level Redundant Detection Technique Based On Domestic Multi-core Processor

The rapid development of integrated circuit fabrication makes the processor’scalculating creditability be threatened by the transient faults. Especially in the ultra-deep submicron level, the probability of occurrence of the transient faults will begreatly increased. At the same time due to the rapid development of computerarchitecture, the microprocessors have stepped into a new era of multicore on asingal chip. So it’s very necessary to do a very deep research on the transient fault-tolerant technology under multicore platform. Study of transient fault-toleranttechnology now has touched into the computer’s processor architecture level,operating system level, application level and compiler level.Faults are firstly introduced in this paper. After make a deep analysis on faultsand their influence level, we introduce different fault-tolerant technologies based onthe computer architecture which include processor-based models, compiler-basedmodels and techniqes, operating system-based models and application-based modelsand algorithms. After make a deep research on different models, we propose aprocess level redundant detection technique based on deomestic multi-core processor.In this paper, we focus on the design of each module in detail, including relatedtechnologies.At the end of this paper, we implement this detection technique in the linuxkernel level based on the domestic loongon processor. Experimental results show thatour detection technique can make full use of the advantage of multi-core processorsto detect transient fault and also meet the performance requirements.