Design Of Key Circuits In14bit250MSPS Pipelined ADC

As the development of digital technique, the high speed and high precision ADCsare becoming more and more important. Taking into account the advantages of speed,accuracy and power consumption, the pipelined ADC is widely used in the high-endelectronic information systems such as cellular base stations in the moderncommunication system, receivers in the imaging radar.The MDAC circuit, sub-ADC circuit and bandgap reference circuit is the keycircuits of pipelined ADC, the accuracy and speed dominant the performances of overallsystem. The thesis studieds on these key circuits and designs the first stage MDAC,high-speed dynamic comparator (sub-ADC), and bandgap reference circuits, which fitthe14bit250MSPS pipelined ADC based on an SMIC0.18μm CMOS technology at1.8V.First, this thesis analyses the structure of pipelined ADC and chooses the SHA-lessstructure for the entire system and a first stage MDAC of3.5bit quantitative accuracy.Then the design of the full differential amplifier with Gain-boost and CMFB, thebootstrapped switch, high-speed dynamic comparator and the bandgap reference circuitsis introduced in detail. Finaly the offline digital calibration is used to improve theperformance of the ADC.Simulation results show that the DC gain of operational amplifier is92.57dB andthe phase margin at13dB is62°. The offset of the dynamic comparator is375μV. Whenthe input signal is100MHz, the SNDR and SFDR are about81.5dB and98dB, and theENOB is13.27bit. The temperature coefficient of the bandgap reference is10.347ppm/℃, PSRR is98.8dB at low-frequency.Finally the simulation results of the entire pipelined ADC indicate that when theinput signal is100MHz and the sampling clock is250MHz, the ADC achieves a SNR of22.16dB, an SFDR of93.4dB, an SNDR of81.13dB and13.18bit of ENOB. The wholepower consumption is300mW. The area of the layout is3.4×4.2mm2.