Research For Calculation Model Based Simulator

With the increasing demand for the better performance of the processor, it becomes a new challenge to validate the correctness and efficiency of the new processor both quickly and efficiently. The architecture simulator is a software tool which can be used to simulate all or part of the behavior the processor. And it can also simulate different kinds of target architecture just by changing its parameters. Therefore the simulator is widely used among the staffs who are researching in processor design and computer architecture.For the moment, the most widely used simulators belong to cycle-accurate simulator, whose design is based on complete detail simulation. Though this class of simulator can ensure the accuracy, but it is always obsessed by long-time development and low speed. Nowadays most researches of simulator focus on optimization of either architecture or performance, but none of them can solve the mentioned problems at one time. Another kind of simulators is based on abstraction model. The major idea of this kind of simulators is to raise the abstraction level in simulation design, which leverages calculation instead of simulation to implement part of or all the functions of the hardware components to optimize the design and performance of the simulator. Interval simulation belongs to such kind of idea based on part of abstraction model. The idea of interval simulation supposes only miss event is the most important reason that affects the performance. So during the process of simulation it only focus on the miss event and ignores the effects of other things, which can raise the speed of the simulator. In order to get the accurate result of the miss event, it should leverage detail simulation over the hardware components which affect the final performance of the target architecture a lot, such as branch predictor and cache. However, interval simulation also involves in some accuracy problems. Because it only focuses on the miss event and ignore the evaluation of the normal instruction stream, the simulator will have a15.62%error rate on reporting the final simulated performance result.We provide a calculation model based simulator with the idea established in a higher abstraction level. We first choose the special modules which will affect the final performance of the simulation seriously from the target architecture and build the corresponding calculation models. Then we leverage these models to calculate each cycle at which one instruction arrives at each pipeline stage, including fetch cycle, schedule cycle, execution cycle, complete cycle and retire cycle, and get the final simulated performance at last. The advantage of our design idea is that we don’t have to establish and implement the detail simulation of both the pipeline and the hardware components (including branch predictor and cache), which can reduce the complexity of the simulator’s design and improve the speed. The major conclusions in this paper include:(?) Analyze the design idea of the pervasive cycle-accurate simulator and find out the main reason which leads to the problem of complex design and low speed in such simulator. Analyze the design idea of interval simulation and point out the difference to our idea.(?) Provide the design idea of calculation model based simulator, and then implement three calculation models according to the elements which affect the final performance of the target architecture seriously based on this idea, including an out-of-order pipeline calculation model, a branch misprediction calculation model and a cache miss calculation model.(?) The experiments show that our calculation model based simulator archives a speedup of22.74X over a cycle-accurate simulator with only an error rate of2.47%of CPI when simulating the same target architecture and reaches1.27MIPS at the real speed, which is78.19%faster than interval simulation.