The Design Of High-level Simulation Platform Based On PowerPC SOC Architecture

The SoC design based on ESL can quickly set up the hardware platform, developand verify the software process rapidly, determine the optimal system architecture andimplement the hardware and software co-design finally. There are two kinds oftechnology of ESL design. One is the method of TLM. Using the SystemC language,we can design the accurate modeling of the hardware behavior, so we can completesystem verification and design space exploration. However its simulation speed can’trun large applications, such as OS and video coding. The other method is virtualtechnology. it focus on the description of the hardware function only, so it has fastsimulation speed and it can run large process. However, it can’t evaluate the merits ofthe architecture result of the rough modeling. How to ensure the accuracy of ESLdesign and improve simulation speed has become a question concern by the field ofSoC design.PowerPC architecture is recognized as the representative of thesecond-generation high performance RISC, but the market is lack of the simulationplatform. Therefore, this paper proposes and design a high level hybrid simulationplatform based on PowerPC SoC architecture. Firstly the SoC designer usuallyconcern the correctness of the relatively stable processor, so we design the instructionset simulation by using the dynamic binary translation technology in the QEMU andexpand the function by transplant vector instruction. Then the accurate modeling andits hardware-behavior simulation for critical PowerPC components is achieved viaTLM. Finally, a software development process is exploited based on PowerPC SoCsimulation platform, which completes hardware-software co-design sufficiently.