Hardware Implementation Of Ldpc Encoding And Decoding In Ofdm Communication Systems

Because of the performance of high spectral efficiency and resistance to intersymbol interference and multipath interference, orthogonal frequency division multiplexing (OFDM) has been widely used in the new wireless communication standards. In this thesis, LDPC codes are introduced into our laboratory FPGA platform of OFDM baseband communication systems to reduce the error rate. LDPC coding which had been put forward in1962by Gallager, was rediscovered in the1990s. It has many advantages:performance close to the Shannon limit, concise form and easy to analyze, low decoding complexity for hardware implementation. The good prospects make it significant to study the hardware implementation of LDPC encoding and decoding.Due to the nature constraints of linear block coding, it is urgently needed to solve the problem that the complexity of the hardware implementation of LDPC encoding and decoding is too high. Because of the special loop form of quasi-cyclic LDPC codes(QC-LDPC), shift registers can be used to simplify the coding structure as well as reduce the matrix storage when decoding. In this thesis, QC-LDPC codes are chosen as the basis for hardware implementation, and some in-depth research into the FPGA implementation of QC-LDPC coding have been done. The main work includes:1.Based on the research into LDPC codes’ theory, the matrix structure of quasi-cyclic LDPC codes is analyzed. Several coding structures are compared. A QC-LDPC encoder which can dynamic continuously encode is designed based on the two stage algorithm, and it shortens the coding delay. 2.After the analysis of the characteristics of several belief propagation decoding algorithms, Mim-Sum decoding algorithm is selected for implementation of decoder on FPGA. The expression of decoding initialization information of16QAM OFDM system is given, and the decoding iteration and fixed length is simulated on matlab.3.We compared different decoding structures, and a semi-parallel QC-LDPC decoder circuit structure implemented by Verilog HDL is designed on ISE software. The decoder can dynamic continuously process data block.4. Data rate conversion between the OFDM baseband system and RF DA/AD is researched, and the baseband transceiver and DA/AD are connected successfully.