A Design And Implementation For High Speed And Soft Error Tolerant CAM

Content-addressable memory(CAM) is a special type of memory. It can not only access data like SRAM, but also perform high-speed parallel search operation. CAM can return search results in one clock period, so it is faster than other hardware-based or software-based search schemes. Therefore, CAM is widely used in search-intensive applications such as look up tables, data compression, image processing etc. With the development of optical fiber technology and the emergence of new features, the growing demond for high-speed networks is pushing the existing solutions to their limits in order to meet the increasing packet processing rates. So the high-speed researching of CAM becomes more and more important.Additionally, SRAM-based CAM is more susceptible to soft errors caused primarily by alpha-particle and neutron radiation. The large di/dt issue during comparison operation reduces operating voltage ranges, which in turn reduces soft error immunity. With the development of VLSI technology, this problem will be getting worse because of the smaller transistor size.In this work, we describe a high speed1-bit soft-error tolerant CAM. The proposed design uses coding to increase hamming distances between words, because of using mismatch-dependent match line structure, the search operation become faster. Moreover,1-bit soft-error in match and mismatch words are distinguished because of the increasing hamming distance. Adding a3-bit Dummy word, our scheme could remove1-bit soft error.Eventually, we simulate a64W×153Bit CAM in130nm1.2V standard CMOS technology. The search time of our scheme is0.7ns and ML power dissipation is0.97fJ/bit/Search, increasing in area is20.7%for the parity bits.