Low Speed Signal’s Accurate Timing Measurement On Transmission Line Load

When a memory product with slow speed 10 is validated and tested for read timing on the transmission line-based automated testing equipment (ATE), an unexpected large measurement error occurs, which is beyond the acceptable testing error range. To solve this problem and make the product be measurable accurately on ATE, a test method based on the transmission line theory and the ratio of signal voltage to power voltage on RC, RLC model is developed, proved and implemented.By means of converting ATE IO trace layout loading from transmission line model to distributed capacitance model, and using RC, RLC model to understand the different capacitance loading impact on IO output signal’s amplitude and timing, a theory is proved that there is always a VOH, VOL as signal voltage threshold, which could be used to strobe silicon output signal to determine ’1’,’0’ and get an accurate read timing result aligned well with the real timing performance with specification required loading. This timing result has an acceptable measuring error. The ratio of VOH, VOL to Vccq (applied power voltage of silicon output buffer) is only dependent on ATE’s distributed capacitance loading and Specification required loading. It is also immune to the impact of silicon’s output buffer impedance variation, ambient temperature variation and unit-unit’s performance difference.Simulation and silicon data matches the theory and expectation. The silicon test result based on this method shows that the silicon’s real read timing performance not only matches the expected data under Spec required test loading, but also keeps the unit-unit’s performance trend to be not changed and each unit’s intrinsic performance feature caused by process or trimming variation. The silicon result matches the expected real performance well under different ambient temperature and applied power supply (Vccq).In the high volume manufacturing (HVM), this method may not cause overkill or underkill by comparing to simple timing derate, so it meets both requirement from high volume manufacturing testing and silicon timing characterization. It creates the capability that the memory product’s read timing could be accurately validated and tested on transmission line-based ATE even if the product has slow speed IO. This solves the low timing accuracy issue in characterization and low yield issue in HVM.