Design Of Analog Front End Circuit In High Speed Optical Communication Receiver

The coming of the data technology era requires higher capability of data storing, processing and transmitting. The challenges on the storage and the data processing are well settled as technology scales down, whereas the data transmitting speed still falls behind which becomes the bottleneck of the big data era. Being widely accepted as one of the best solution to the big data transmitting challenge, the optical communication shows great potential and momentum in recent years. Consequently, many efforts have been made in the research on high integrated density and low power optical communication receiver working beyond tens of gigabit per second. In this work, an analog front end circuit in high speed optical communication receiver has been presented. The main works of this thesis are as following:First, the general architecture and basic conception of optical communication system are presented. The impact of critical parameters on the PseudoRandom Binary Sequence (PRBS) has been studied as the guidance for the subsequent circuit design.Second, the limiting amplifier has been selected as the main amplifier after a careful comparison with other amplifiers. It achieves the broaden bandwidth and flatness response by employing the active interleaving feedback technique. System stability is analyzed based on the poles and zeros. In consideration of the large DC offset with 65nm technology, an error amplifier with cancellation loop is proposed to eliminate such effect. Fabricated in TSMC 65nm CMOS technology, the limiting amplifier only occupies an area of 0.11mm2. The measurement results show that the limiting amplifier achieves differential voltage gain of 37dB and a-3dB bandwidth of 16.5GHz. Up to the 26.5GHz, the Sdd11 and Sdd22 are less than -16dB and -9dB. Excluding the buffers, the chip is driven by 1.2V supply voltage and draws 50mA current.Finally, architectures of transimpedance amplifier are compared. In this design a common gate circuit with feedback is selected based on the analysis and optimization of noise, bandwidth and power consumption. Simulation results show that the transimpedance amplifer achieves a transimpedance of 48dB Ω, a-3dB bandwidth of 28GHz with the integrated input referred noise to be 3.75uA. Up to the 31.5GHz, the Sn is less than-10dB. With 1.2V supply voltage, the circuit consumes 10.8mA current. The whole analog front end exhibits a-3dB bandwidth of 18.8GHz with the gain of 88dB Ω.