On-wafer De-embedding Techniuques From 0.1 GHz To 110 GHz

The process of de-embedding consists in shifting the electrical reference planes closer to the actual DUT in order to subtract unwanted contributions. For on-wafer measurements, either the passive components or the active devices need the dedicated on-wafer test structures to obtain the microwave behavior. However, the extrinsic parasitics of test structures, such as the contact pads, the metal interconnections and the substrate, greatly impact the microwave behavior of the actual DUT. With the available operation frequency of circuits and devices increasing into tens or even hundreds of gigahertz, the extrinsic parasitics of DUT become more and more complex. Therefore, in order to remove the parasitics of DUT and obtain the actual behavior of intrinsic DUT, the de-embedding techniques are increasingly important.The on-wafer de-embedding techniques from 0.1 GHz to 110 GHz on InP substrate basing on thickness of 450μm and 50μm are researched in this thesis. The main investigations are TRL and LRM techniques. The design of de-embedding structures is based on co-planar waveguide (CPW), which is relatively simple basing on conventional thichness of InP substrate. If the thickness of substrate is reduced, the transmission mode in CPW will change, and the design of de-embedding structures will change correspondingly.Firstly, two matrix operation methods TRL and LRM, basing on the transmission line theory, are realized. Because they do not require the equivalent lumped circuit model, the two methods can be used as on-wafer S-parameter de-embedding methods for high-frequency devices. Based on the symmetric algorithms, the asymmetric de-embedding algorithms of TRL and LRM are derived and the detailed soving results are given.Secondly, the on-wafer de-embedding from 0.1 GHz to 110 GHz on InP substrate basing on thickness of 450μm is performed by TRL and LRM methods. Two passive components interdigital capacitor and open-stub are designed to demonstrate the validity of TRL and LRM de-embedding techniques. The de-embedding results of the two methods are also compared. The on-wafer measurements show that both the two methods can be applied to extract the intrinsc parameters accurately from 0.1 GHz to 110 GHz, but the LRM de-embedding results agree better with the simulations in lower frequency and TRL is more accurate in higher frequency. The active device HBT basing on 450μm thick InP substrate is de-embedded by the combination methods of TRL and LRM, and the intrinsic parameters of HBT from 0.1 GHz to 110 GHz are given.Finally, the on-wafer de-embedding from 0.1 GHz to 110 GHz on InP substrate basing on thickness of 50μm is researched. When the thickness of InP substrate is reduced to 50μm, the parasitic parallel-plate mode of transmission in co-planar waveguide emerges. In order to remove the parasitic parallel-plate mode, a row of via holes uniformly arranged is symmetrically added in the ground planes of co-planar waveguide in design of de-embedding structure patterns. Meanwhile, the de-embedding structures without via holes are designed as reference, and the passive component interdigital capacitor is designed to demonstrate the validity of de-embedding results. The measurements agree well with simulations when using the de-embedding structures with via holes in 0.1 GHz-110 GHz, but it give bad results using the de-embedding structures without via holes. Then the active device HEMT basing on 50μm thick InP substrate is de-embedded on-wafer by the designed de-embedding structures with via holes, and the intrinsic parameters of HEMT from 0.1 GHz to 110 GHz are given.