Design And Study Of Bufferless Network-on-chip

Compared with off-chip network, chip area, power consumption, and implementation complexity are the first-class hardware implementation constraints of Network-on-Chip(No C). However, a high proportion of chip area and power consumption is consumed by the buffers in the input ports of router. In order to solve the problem, the bufferless No C, which eliminates in-router buffers and copes with contention by deflecting packets/flits, has been proposed. The bufferless No C has been shown to operate efficiently under low or moderate workload, owing to infrequent deflections. Nevertheless, under high workload, frequent deflections lead to deterioration of performance. Therefore, how to reduce the deflection probability is the key issue of designing bufferless No Cs.This thesis summarizes the background and development of No C, and conducts a systematic research on the critical techniques of bufferless deflection No Cs. Our research achievements are shown as follows.1. The existing bufferless No C designs do not provide Quality-of-Service(Qo S) guarantees. In this thesis, we propose a Qo S-aware Bufferless No C, named QBNo C. QBNo C employs hybrid switching mechanism, namely circuit switching mechanism for real-time application and wormhole switching mechanism for other applications. Besides, in order to decrease the deflection probability and thus improve the performance of the network, we propose a new output port allocation policy. Furthermore, new router architecture with shorter critical path is designed for QBNo C. The evaluation results show that by efficiently exploiting resources, our proposal significantly improves the performance of the whole network, and meanwhile satisfies the Qo S requirements of different applications.2. In optical No C using packet switching mechanism, considering no mature optical buffering technology, deflection routing is preferable to resolve the output port contention. This thesis proposes a new 5*5 router architecture, and especially a deflection-supported switching fabric. Moreover, an ejection unit and an injection unit are designed to reduce the deflection. Additionally, priority-based routing computation and port allocation algorithms are designed based on the new switching fabric. The simulation results show that our proposal can improve performance at acceptable insertion loss.