Design And Implementation Of Timing Control Circuit For XXX Distributed Radar

With the stealth weapon appearing, all kinds of new type of detection systems and precision-guided weapons get the attention of more and more countries. To meet the urgent demand of the air defense in our country, a distributed meter wave radar system is proposed. The distributed meter wave radar system is a new generation of air defense weapon system, which is developed for effectively combat stealth aircraft. It is a comprehensive system with computer interactivity, processing, distribution and feedback real-time technology.To verify the advancement and feasibility of the key technologies of the XXX distributed radar system, a system of theoretic experiments is built according to the characteristics and practical requirements of it. The system of theoretic experiments consist of a clock frequency source, a power divider, two meters wave digital array modules(DAM), two correction networks, two array antennas, a timing control subsystem, a PC, a data collector and a signal processing board. As the sequential control center subsystem of the system, a timing control subsystem with multiple high-speed data transmission interfaces and strong data processing ability is needed,which is studied in the Paper.The architecture of the system of theoretic experiments is described, and the main functions of the timing control subsystem are analyzed, which are producing the entire system timing control signals, high speed data exchanging with meter wave digital array modules by optical fiber, controlling DAMs to produce the required waveforms and timing, communicating with PC through the communication interface batch and accurately to implement the data upload, parameter and working mode and waveform instructions receiving, the system timing reference clock generation. Based on the function of the timing control subsystem, the overall design scheme and module partitions of it are given. The various modules structure, parameters, performance and other technical question are analyzed and discussed in detail. Finally the timing control system hardware principle diagram design is discussed. The Integrity of some special request signals is simulating and the PCB is designed and tested.Two main communication interfaces in the timing control subsystem are discussed:(1) the high-speed Ethernet communication module: the transceiver logics in FPGA are designed and simulated, and the debugging results show that the design scheme is correct. To solve the problem of possible displacement in data, a special program module is designed. Relevant processing results also verify the feasibility of design scheme.(2) USB 2.0 interface: its firmware program logic framework and control requirements are analyzed, and the firmware program is designed and realized for the system of theoretic experiment. According to the requirements of the transmission firmware program, the FPGA control interface program is designed in detail, and the debugging results are described, that verify the validity of the design.The debugging and testing to the timing control hardware circuit and the corresponding interface shows that the whole timing control hardware circuits design and functional testing based on FPGA + DSP is completed. The research results are used in the system of theoretic experiments. And it implements the production of the whole system timing control signals, the required waveforms and sequence to control DAMs, and the data upload and download, etc,and the design is in good condition.