Design And Implementation Of High-speed Electronic Storage Array Based On SATA Interface

With the development of science and information industry, the increasing demand for the accuracy of recording high speed RF signal makes the duration of signal acquisition and the sample frequency grows. In order to record the acquired signal completely and in real-time, it’s necessary to develop a storage equipment of high speed and of large capacity. Furthermore, the equipment should be operated offline and easily carried to adapt to outfield test environment.In order to satisfy these requirements, the paper puts forward the system architecture for high speed memory array after analyzing specific needs and studying the storage technology deeply. The system architecture has been already applied in scientific research project. The storage system is integrated in one piece of Virtex-5 FPGA, with embedded hardcore Power PC440 as control part and the EDK as development environment. And the storage medium of system is solid state disks which are compatible with SATA and RAID0. The disk array works in parallel as many SATA controllers instantiated. The main work is as follow:1. SATA 2.0 protocol is studied and analyzed. And on this basis, the paper integrates the SATA controller’s physical layer、 link layer 、transport layer and bus interface as user IP. Then, the paper develops the storage system based on embedded SATA controller in EDK, using FPGA as developing platform and Power PC440 as processor. The paper not only realize the command transmission protocol of SATA protocol but also the control of whole system by programming the PPC440 processor in C language. At last, the paper tests the embedded storage system’s performance. The transmission error number is zero;the writing speed is about 200MB/s and the reading speed is about 275MB/s.2. According to the storage requirements for the project, the high-speed electronic storage array architecture is proposed based on embedded storage system with single SATA controller. The system instantiates eight SATA controllers mounted to the system bus on a single FPGA. All SATA controllers work in parallel, composing the disk array of RAID0 level. In order to match sampling rate and data storage rate, the paper designs a cache unit using multi DDR2, all of which work alternately. The system uses the MPMC to read and write the DDR2 cache array directly, which separates the transmission of control information from data. In order to further improve the memory bandwidth, the paper adopts pipeline data allocation strategy, and design the data distribution module to allocate data.3. The control logic is designed to read /write cache under the control of PPC440. The system works as follow: in storage process, the AD module inputs data by GTX. And the data distribution module writes data to DDR2 array after distributing. The SATA controller group reads data from DDR2 directly and write data to hard disk array under the control of PPC440. When PC reading the data back, the SATA controller group read data from the disk array and write to DDR2 after data distribution module splicing data. The GTX upload data to PC.4. The custom file system is designed to implement data the management of hard disk array. The file system uses continuous storage methods, and divides the whole space into three parts, as the boot sector、file directory and data blocks. According to the specific requirements of the project, the paper defines command protocol interacting with PC, which completed by RS232 protocol. The file system has these basic functions as writing file、reading file and deleting file, and has the advantages of high-speed、simple and so on.5. The performance of high-speed electronic storage array is tested. The array is composed with eight SSDs with the RAID0 mode, and the speed of writing is about 1.6GB/s, the speed of reading is about 2.1GB/s; the file system can work well.