Application Research Of UVM Verification Methodology For Wireless Sensor Network

With the continuous increase of So C scale, the complexity of system verification is increasing too. Thus traditional verification methods are difficult to make the verification completed, which has become a bottleneck restricting the development of So C technology. In order to reduce the gap between it and the design and manufacture industry, a series of advanced verification methodology and verification language has been developing rapidly. UVM(Universal Verification Methodology) verification methodology is a powerful verification methodology, which developed by many industry experts in order to meet their own R&D requirement. Researching and applying UVM verification methodology are of important practical significance.This paper studies the method to build reusable and automatic verification platform based on UVM verification methodology and System Verilog language. And use this platform to verify the function of transmission subsystem of Zig Bee wireless sensor network chip. The paper makes an in-depth research on UVM verification methodology, verification platform design and transmission subsystem of wireless sensor network, etc. The concrete research contents and main harvests are as follows:1. This paper makes a detailed analysis of UVM verification methodology, including concepts covered, important mechanisms, its advantages and basic framework. Based on the analysis of the overall structure of the verification platform, this paper design a 5 layer function model of universal verification platform with top-down design method, which include the top layer, the testcase layer, the environment layer, the function layer and the signal command layer. The platform passes the signal parameters by ports between each layer.2. This paper makes a detailed analysis of the protocol, interface and the basic function structure in the transmission subsystem of wireless sensor network chip to be test. And then put forward the DUT’s function point to be tested and corresponding verification scheme. The paper also presents the overall structure of the transmission subsystem’s verification platform.3. According to the design method and structure of verification platform, the paper build a verification platform which is used to verify the transmission subsystem of wireless sensor network, and complete the design of verification environment’s components at each level, the components include the information transmission class, the command signal layer’s components, the agent, the reference_model, the scoreboard, the environment layer’s component, the testcase layer’s component, etc. And then the paper makes a detail analysis for the reusability of the verification environment.4. This paper makes the design and implementation of the wireless sensor network’s verification platform based on UVM and the language of System Verilog. And test it with Model Sim. The verification results including the scoreboard’s output which is the comparison of standard results and results to be tested, the simulation waveform for observing the DUT’s input and output and the coverage calculation. The simulation results show that the function point analyzed in this paper are all covered, statement coverage rate reached above 90%. The results show that the transmission subsystem of Zig Bee wireless sensor network chip can accomplish its intended function accurately, and confirm that it can efficiently design a strong reusability, scalability and high automaticity verification platform based on UVM verification methodology.This paper’s platform build followed UVM verification methodology, and has a high reusability. It can provide a reference platform for related project.