Backend Design Of Digital Circuit Of National Standard UHF RFID Chip

RFID(Radio Frequency Identification) technology, which emerged in 1980 s and then developed rapidly, is a kind of wireless automatic identification technology. It uses the wireless radio frequency signals to identify a particular item and then reads or writes to it, and this process requires neither human involvement nor needs mechanical or optical contact with the item. With the development of the integrated circuit industry, the low and high frequency RFID technology have been applied throughout our lives, but the UHF RFID technology is in a rapid development stage now.The air interface protocol of national RFID 800/900 MHz is the first UHF RFID standard of our country, which began to be implemented on May 1, 2014, and then some well-known domestic companies began to develop the corresponding products. The main content of this thesis is back-end design of digital integrated circuit based on this national standard protocol. The back-end design is the essential process of realizing chip successful manufacturing.This thesis first analyzes the background and significance of proposing the protocol of national standard UHF RFID, and then briefly introduces the main content of this protocol. Secondly, the back-end design flow based on Synopsys IC Compiler is discussed in detail, generally including design data preparation, building design library, timing setup, floor planning, placement, clock tree synthesis, routing and design for manufacturability. Finally, we use Synopsys Prime Time tool for static timing analysis, Synopsys Formality tool for formal verification, and Synopsys VCS tool for the post simulation. Moreover,the DRC and LVS check of UHF RFID full chip layout is done by Calibre tool from Mentor Graphics.The verification results show that the digital layout passes the static timing analysis, formal verification and post simulation, and the UHF RFID full chip layout passes the DRC and LVS check,so the GDSII format file of this full chip layout can be submitted to the SMIC foundry for production. The full chip is fabricated in SMIC 0.18μm 2P4 M EEPROM process, which is one of the most advanced EEPROM process now.