The Design Of High-speed Timing Data Synthesis Module

The Data Generator has been widely used in modern measuring and controlling fields, it can generate kinds of programmable user data to meet some special digital measuring requirements. With the rapid development of modern science and technology level, the working speed of the equipment is improved and its system function is also becoming more complicated, So that the development of modern electronic technology requires the data generator to be provided with faster data rate, deeper memory depth,greater programmability and picoseconds timing. In this paper, discussed in detail high speed data stream generating and completed the design of high-speed timing data synthesis module. Finally the high speed double channel data flow produce system with 2.7 Gbps data flow output rate and single channel 256 Mbits storage depth is achieved.As the core of data generator, The high-speed timing synthesis module undertakes the role of generating serial data stream signals of different frequency under three operating modes of repeat、single and single-step,and achieving data rate and timing delay adjustment. This paper describes how to generate high-speed data stream of faster data rate、deeper storage depth and under kinds of operating modes.The main works of this paper include:(1) Illustrates the principles and methods for data synthesis, and put forward the whole grogram of high-speed generation according to the requirements of functions, indicators and difficulties of design.(2) Complete the design of clock generating part: by using DDS combining with PLL project to achieving 50 KHz~2.7GHz clock output.(3) Complete the design of data stream to synthesis and control module. The design takes use of dynamic memory technology, and combined with FIFO to cache data to achieve serial data stream with deeper storage. In this part, the project use large capacity of DDR memory to achieve the deep storage of 256Mbits; use asynchronous FIFO to realize data rate conversion and timing control; use technology of parallel to serial to complete high-speed serial data generating with 2.7 Gbps rate; using programmable delay chip with high resolution to achieve double channel delay timing accuracy and high resolution.(4)Analyze each sub-module actual work based on signal waveform. Troubleshooting the problems found during debugging, and some feasible solutions are also given. At last test and acceptance the whole project and program, at last Organize related documents.In this paper, by studying the key technology, completed the module design and debugging, finally the the high speed data flow output in variety of trigger patterns and operation mode is achieved, completed the design goals.