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Passive Uhf RFID Tag Chip Analog Front-end Design And Verification

Posted on:2015-12-25Degree:MasterType:Thesis
Country:ChinaCandidate:J Z ChenFull Text:PDF
GTID:2308330473452102Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Radio Frequency Idendtification(RFID) is one of the fastest growing and most benefical technologies being adopted by businesses today. The technology has been widely used in identity authentication, smart appliances, logistics systems, access control and security management systems, automotive examiners, food control, campus card world, library management, implantable biomedical devices and many other fields. Since the UHF RFID system has fast data transfer rates and smaller antenna size relative to the high-frequency RFID systems, it has been become the most talked about RFID technology within the industry. For the research and application of passive UHF RFID systems started later than abroad, in China. Therefore, this paper has important significance for the study of passive UHF RFID tag chip analog front end.Firstly, by analyzing the EPCglobal Class-1 Generation-2 protocol, this paper describes the data transmission principle of passive UHF RFID systems, energy transfer principle and maximum power implementation, and then on this basis proposed the system architecture of passive UHF RFID tag chip and technical targets of the each module of the chip analog front-end.Secondly, according to the technical targets of each module, completed design modules, simulation and optimization of the passive UHF RFID tag chip analog front end, including a boost rectifier circuit, limiter circuit, reference circuit, Voltage regulator circuit, a demodulation circuit, a clock generation circuit and the power-on reset circuit. To meet the requirements of low power design, the reference circuit using subthreshold technique. Provides current bias current reference for other circuit blocks with only a hundred nA, effectively reducing the power consumption. Simulation results show that the chip analog front end circuit consumes a total current of less than 3μA.Then, this paper uses GSMC 0.18μm CMOS 1P5 M process completed chip layout design and end-simulation. The size of chip area is 870μm × 1160μm.Finally, designing of the chip test PCB, and samples were tested and recorded data. The test results showed that the basic realization of the circuit function modules, but there are still some deficiencies that need to be further improved.
Keywords/Search Tags:UHF, EPCglobal Class-1 Generation-2, RFID, analog front end
PDF Full Text Request
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