Design Of The Programmable Analog Baseband Filter For Single-chip UHF RFID Reader

UHF RFID technology has been widely used in many kinds of service industries,on account of its advantages of fast transferring rates,large storage capacity and long distance reading. This paper aims to study and design the analog baseband filter for CMOS single-chip UHF RFID Reader.The results of the research are as follows:Firstly,a variety of methods to design analog filter are studied and compared. To meet the requirements of analog baseband for UHF RFID Zero IF receiver,this paper design a channel selection filter whose cutoff frequency is adjustable from 84 kHz to 1.55 MHz. Taking into account the requirements of linearity and attenuation,the filter employ fourth-order fully differential chebyshev Tow-Thomas structure. Because the channel selection filter’s cutoff frequency needs very high accuracy,this paper designs an automatic frequency calibration circuit which presents simple structure and high accuracy. On the base of TSMC 0.18μm CMOS mixed-signal process,this paper accomplishes the design of the circuit and layout. The post simulation results display that the filter’s cutoff frequency can be set in eight different frequencies: 86.27kHz、168.6kHz、354.8kHz、448.4kHz、579.7kHz、684.3kHz、714.3kHz、1.59 MHz,and the out of band IIP3 achieves 31.14 dBm.Secondly, to meet the requirement of voltage gain of the receiver analog baseband, this paper design a Programmable Gain Amplifier(PGA) which can obtain a voltage gain range of 58 dB. Because of the existence of DC offset in Zero IF receiver,the Dc Offset Cancellation circuit must be applied in the PGA. The results of post-layout simulation show that the PGA’s voltage gain can vary from 0 to 58 dB by a gain step of 2dB and gain error less than 0.5dB;It achieves-40 dB attenuation near DC and the in band IIP3 achieves 27.83 dBm.Thirdly,this paper designs a fifth-order chebyshev low-pass filter to meet the requirements of analog baseband for UHF RFID direct conversion transmitter. The filter is used to suppress the mirroring spectrum interference generated by the former circuit DAC. The voltage gain of the filter is obtained by controlling the resistor array to adjust the signal amplitude of DAC output. The results of post-layout simulation show that the filter’s-3dB bandwidth is 613.8KHz,and the out of band rejection of image frequency interference near 6.5MHz reaches 116 dB.The filter’s voltage gain can vary from 0 to-8dB by a gain step of 0.5dB and gain error less than 0.1dB.