A Partial Scan-chain Based Security Test Method For Cryptographic Ics Against Fault Injection Attack

With the rise and development of Data Mining, Internet of Things, Cloud Computing and Smart Home, the scope and depth of the well known Internet continues to expand. Information security has also become an increasingly important technology and social issues. Cryptographic ICs have been widely applied to numerous security-critical environments nowadays to protect the information security.Fault injection(FI) has become a serious attack on cryptographic ICs. However, the test on the cryptographic ICs against fault injection(FI) attacks is still sample test rather than large volume test due to the difficulty in effective fault injection. If the security of cryptographic ICs can not be tested and confirmed, the whole information security is weak.This paper proposes a novel partial scan method for security test. This paper exploits the Design for Test technology into the security test of cryptographic ICs. The method involves the automatic soft error simulation platform to select the FI security-critical registers by calculating the Soft Error Rate. With the selected registers inserting into the scan chain, we can enhance the observability and controllability.In the mean while, the paper proceeds from the fault injection attack theory to select sensitive registers, the method makes the selection of registers more reliable. With the selected registers inserted into the scan chain, we make partial scan chain compiling and test pattern generation.The experimental consequence on an AES reference circuit demonstrates that the proposed method is efficient with small area overhead and feasible to large volume test...