The Research On Low Power Test Methods Based On Linear Decompression Structure

With the development of semiconductor manufacturing technology, the integration of chips becomes higher and higher, resulting in more and more functions are integrated on a chip. However, high integration also brings great challenges for VLSI testing. A large amount of test data and high test power consumption has become the problem that industry and academia eager to solve. This thesis analyzes the reasons and the harm for high test power consumption, and describes some test data compression methods and low power test methods which have been proposed. The thesis also points out the contradiction between the test data compression technology and low power test technology. Two low power test data compression schemes have been proposed on this basis.For the problem of how to balance test power and coding efficiency in LFSR reseeding, this thesis proposed a low power scheme which first uses compatible block code to optimize the test cube, and then merges the flags of test cubes, finally LFSR reseeding is applied. During encoding, firstly, in order to reduce the number of specified bits and the test shift power, the scheme divides a test cube into blocks of different types and uses the flag to distinguish. Then the x bits in flags are used to reduce the specified bits in a test cube continually by merging compatible flag. According to the compatibility of flag, the scheme proposes a grouping algorithm based on flag to divide and reorder the test cubes in the test cube set. Experimental results on ISCAS-89 benchmark circuits indicate that the scheme can obtain better test compression ratio and reduce the test power consumption effectively. The average compression ratio is 94.15%and the average reduction of average power is 75.18%.The coding efficiency of test data compression based on Viterbi algorithm is higher and independent of the number of test channels. But the Viterbi test compression method causes high test power and the coding efficiency will drop when a test set contains many specified bits. This thesis proposes a low power test compression scheme based on Viterbi algorithm. Firstly, a few x bits in a test cube are used to reduce test power, for enhancing the consistency between adjacent bits of the cube. Then in order to increase the number of x bits and improve the coding efficiency of Viterbi compression, lots of specified bits are encoded to x bits again by compatible block code. Finally, use Viterbi algorithm to compress the test cube set after coding. This thesis builds a test process that can solve the problems of test compression and test power at the same time. Experimental results show that the scheme can increase test compression ratio and reduce the test power consumption effectively.