Research And Implementation Of Anti-jamming Algorithm In GNSS Baseband Chip

As the GNSS system constantly developing in recent years, it gets more and more widely used in military and civilian two areas. And then, it produces great benefits to the society and economic. However, due to GNSS signals are propagated from more than 20,000 kilometers in space to the ground, the received GNSS signals’ power is already very fragile and the signals are vulnerable to interference. Especially in the military, if the interference imposed by the enemy can not be resisted effectively, the receiving devices can not complete the GNSS signals’ acquisition and tracking. So, goverments of many countries attach great importance to anti-jamming technologies research.Now, there are many researches on the GNSS anti-jamming algorithm and the researches on implementing anti-jamming algorithems by ASIC are relatively few. Some algorithems that can implement by hardware apply in practice currently mainly based on FPGA. The purpose of this thesis is to study a single GNSS baseband chip that can simultaneously suppress strong narrowband and wideband interference, to design its hardware arctecture and to do front-end implementation and functional verification. Given the long-term and complexity of the study of anti-jamming algorithms and baseband chip design and implementation, the research object of this thesis is interference with strong power. Focusing on one kind of time-spatial processing scheme and two types of frequency-spatial processing method, the thesis gives the comparison and analysis from the resource, area and power, and ultimately selected the threshold-detection frequency domain algorithm as the GNSS baseband chip implementation. The implementation overall structure is given in the thesis. First, its feasibility is verified by the algorithm level design. Subsquently, the specific and detailed implementation of every functional units of the structure are given, together with the corresponding hardware simulation results. Finaly, the functional simulation and verification of the whole GNSS baseband system are given, and the chip is implemented on FPGA. Further, the thesis gives the experimental test results and verifies the correctness of the design.Now, there is not an anti-jamming technology can “immune” to all types of GNSS facing interference, and one anti-jamming technology can only suppress one specific interference type. Therefore, this paper’s method is a combined anti-jamming algorithm of frequency-domain and spatial-domain for the suppressiong of narrowband and wideband interference. Now, joint domain anti-jamming technology has been one of the future development directions of the researches on anti-jamming algorithms. And joint domain anti-jamming technologies ASIC designs and implementations have not seen the related presentations. So, this paper’ work can also be seen as an attempt and exploration of the ASIC design and implementation of joint domain anti-jamming technologies. And it has a good practical significance of the research and application of anti-jamming technology.