Low Power Physical Design Of Optical Communication Chip Under 28nm Process

With the development of process, today’s SOC(System On Chip) chip requires the smallest area, higher performance, and more reduced power depletion. Firstly, chip requires reduced power depletion values, so that the device can work longer, then requires a better voltage drop to guarantee circuit’s performance. With the incoming of 28 nano technology, the power component has been changed, the designers should respond to these changes actively, pay attention to the details of design, dig and try new ways to optimize power depletion. With the evolution of nano technology, the chip area and net width are smaller and smaller, but the power denseness is more serious. It brings a great challenge to back-end physical designers.Firstly, we analyze the structure and the mechanism of power from the physical level of design, then elaborat the structural changes of power consumption with the development of process. And then we do detail research on the low power methodology from the system architecture level, register coding level, low power synthesis level.The circuit level low power design is the low-power strategy of physical implementation. In the third chapter, we do physical design for a 28 nm low power optical communication chip. Due to the operating frequency is up to 2.7GHz, the power and voltage drop will be a great bottleneck to the performance. We focuses on ADC subsystem level physical design, elaborat the process of the project, including floorplan, powerplan, place, low power clock tree synthesis, post clock tree synthesis optimization, route, static timing analysis, physical verification. We mainly talk about the problems and solutions.Finally, we summarizes the low-power strategy and power analysis results of the physical design. High Vth std_cell ratio reached 85%, and leakage power consumption reduced by 35%. Voltage drop is also expected to the initial targets.